Abstract: In a digital computing system with a central processing unit (CPU) and random access memory (RAM), an improved data access limitation and protection subsystem protects data stored within predetermined boundaries of the RAM. An operation code detector detects a unique operation code stored in the RAM and fetched by the CPU, and puts out a signal when the unique operation code is detected. An address latch stores a high and a low digital boundary address put out by the CPU when the address latch is enabled by the signal from the operation code detector. An address comparator compares digital addresses subsequently put out by the CPU with the stored boundary addresses and puts out a signal as the result of the comparison. The address comparator signal controls a switch which enables or disables an address transformer and a bi-directional data transformer.