Abstract: A method of etching an organic antireflective film layer underlying a patterned resist layer on a semiconductor substrate by contacting the exposed organic film with a fluorocarbon and nitrogen etchant in the presence of a plasma-generated energy and removing exposed areas of the organic film with the etchant. An oxide layer underlying the organic film layer is substantially undamaged after contact with the etchant. The plasma is a high density plasma and preferably contains argon, C4F8, and nitrogen.

Abstract: A silicon article including a silicon base and columns extending from the silicon base. The columns define a gap between the columns which is devoid of material so that the article can act as a filter or heat sink. Also disclosed is a method of making the silicon article.

Abstract: An integrated circuit and method of making the integrated circuit. Air gaps are formed between surfaces of current-conducting lines that face one another and dielectric material disposed between these surfaces of the current-conducting lines. A liner material is applied to these surfaces of the current-conducting lines and, after the dielectric material is introduced between the current-conducting lines, the liner material is removed, for example by etching, leaving air gaps between the current-conducting lines and the dielectric material. These air gaps eliminate or greatly reduce the effect of capacitive currents across the dielectric material between the current-conducting lines.

Abstract: The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks.

Abstract: A silicon article including a silicon base and columns extending from the silicon base. The columns define a gap between the columns which is devoid of material so that the article can act as a filter or heat sink. Also disclosed is a method of making the silicon article.

Abstract: A method for depositing materials on a surface, having the following steps: a) obtaining a surface having at least feature thereon, the surface and the feature having a layer of first material deposited thereon, the first material not filling substantially all of the feature; b) depositing a layer of a second material on the first material, wherein the melting point of the second material is less than that of the first material, and wherein the first material is soluble in the second material at a temperature less than the melting point of the first material; and c) heating the surface to a first temperature of at least equal to the melting point of the second material and at most equal to the melting point of the first material, wherein substantially all of the via is filled with the first material.

Abstract: The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks.

Abstract: Metal silicide is removed at a faster rate than polysilicon in dry etching of metal silicide/polysilicon composites with an etching gas made from HCl and Cl.sub.2 at a volumetric flowrate ratio of HCl:Cl.sub.2 within the range of 3:1 to 5:1.

Abstract: The present invention provides an improved semiconductor ridge waveguide laser structure having a plurality of layers including an N-InP buffer layer and an N-type InP substrate, a thin InGaAsP active layer 1100 Angstroms thickness, a P-InP graded layer, an optional etch stop layer, a P-InP cladding layer and a P+InGaAs. The ridge waveguide laser of the present invention demonstrates a very high reliability and the fabrication process therefor is high yield. The ridge waveguide laser of the present invention demonstrates very good high temperature behavior and the design suppresses higher order modes.

Abstract: A protection configuration for a semiconductor ridge waveguide laser structure is disclosed wherein layers of protective metal in the form of walls, is applied on each side of the ridge element of the ridged layer of the laser structure. The laser structure is then bonded to a mounting plate in a junction side down orientation by solder or a junction side up orientation by wire bonding. The metal layer may be composed of gold.

Abstract: A process for forming the ridge structure of a self-aligned InP-system, double heterostructure (DH) laser, particularly useful for long wavelength devices as required for signal transmission systems includes a thin Si.sub.3 N.sub.4 layer (41) inserted between a photoresist mask (42) that defines the ridge structure, and a contact layer (35). Using a Si.sub.3 N.sub.4 layer (4) deposited at a high plasma excitation frequency (RF) for adhesion promotion, and a low frequency deposited (LF) Si.sub.3 N.sub.4 layer (43) for device embedding, provides for the etch selectively required in the process step that is used to expose the contact layer to ohmic contact metallization deposition.

Abstract: Process for producing temperature-stable undercut profiles for use in semiconductor fabrication. The process is based on the phenomenon of high etch-rate selectivity between RF- and LF- PECVD-grown silicon nitride films (12G and 13G, respectively) that are deposited on top of each other. By choosing proper film and process parameters, these PECVD nitride structures can be made stress-free: the tensile stress of the RF film (12G) compensates the compressive stress of the LF film (13G).Also disclosed is an application of a T-shaped structure (15), produced with the new process, in a method for fabricating fully self-aligned "dummy" gate sub-micron MESFETs.