Abstract: Systems and methods for performing data transfer between first and second electrical devices are provided. One method may include electrically coupling the first electrical device to a first electrical-optical (E-O) device via a first plurality of electrical lanes, electrically coupling the second electrical device to a second E-O device via a second plurality of electrical lanes, optically coupling the first and second E-O devices via a plurality of optical lanes, and transferring data therebetween via a first optical lane. The method may include monitoring one or more parameters associated with an optical transmitter of the first optical lane, and comparing each parameter to a respective threshold. Responsive to the comparison, the method includes commencing transfer of data between the first and second E-O devices via a second optical lane, and terminating transfer of the data between the first and second E-O devices via the first optical lane.

Abstract: Systems and methods for performing data transfer between first and second electrical devices are provided. One method may include electrically coupling the first electrical device to a first electrical-optical (E-O) device via a first plurality of electrical lanes, electrically coupling the second electrical device to a second E-O device via a second plurality of electrical lanes, optically coupling the first and second E-O devices via a plurality of optical lanes, and transferring data therebetween via a first optical lane. The method may include monitoring one or more parameters associated with an optical transmitter of the first optical lane, and comparing each parameter to a respective threshold. Responsive to the comparison, the method includes commencing transfer of data between the first and second E-O devices via a second optical lane, and terminating transfer of the data between the first and second E-O devices via the first optical lane.

Abstract: In at least some embodiments, an electronic device includes a processor and a memory coupled to the processor. The electronic device also includes a serial communication link controller coupled to the processor, the serial communication link controller supporting dynamic reconfiguration of a plurality of communication link bundles. The serial communication link controller receives an input clock and generates first and second clock signals based on the input clock, the first and second clock signals having different clock rates and being provided to each of a plurality of communication link bundles.

Abstract: A system and method for detecting electrical idle in a receiver is disclosed herein. A receiver includes a differential receiver, an analog idle detector, and a first filter. The differential receiver receives a variable rate differential signal. The analog idle detector is coupled to the differential receiver. The analog idle detector provides a first idle signal that erroneously identifies a differential signal electrical idle state. The first filter is coupled to the analog idle detector. The first filter processes the first idle signal and generates a second idle signal lacking the idle state errors of the first idle signal. The first filter provides the second idle signal to receiver control logic that controls signal reception.

Abstract: In at least some embodiments, an electronic device includes a processor and a memory coupled to the processor. The electronic device also includes a serial communication link controller coupled to the processor, the serial communication link controller supporting dynamic reconfiguration of a plurality of communication link bundles. The serial communication link controller receives an input clock and generates first and second clock signals based on the input clock, the first and second clock signals having different clock rates and being provided to each of a plurality of communication link bundles.

Abstract: A system and method for loopback self testing. A system includes a host device and an endpoint device. The host device transmits unencoded test symbols. The endpoint device loops back the unencoded test symbols to the host device. The host device drives at least some bits of each unencoded test symbol onto host device data signals and drives at least some bits of each unencoded test symbol onto host device control signals.

Abstract: A system and method for loopback self testing. A system includes a host device and an endpoint device. The host device transmits unencoded test symbols. The endpoint device loops back the unencoded test symbols to the host device. The host device drives at least some bits of each unencoded test symbol onto host device data signals and drives at least some bits of each unencoded test symbol onto host device control signals.

Abstract: A system and method for detecting electrical idle in a receiver is disclosed herein. A receiver includes a differential receiver, an analog idle detector, and a first filter. The differential receiver receives a variable rate differential signal. The analog idle detector is coupled to the differential receiver. The analog idle detector provides a first idle signal that erroneously identifies a differential signal electrical idle state. The first filter is coupled to the analog idle detector. The first filter processes the first idle signal and generates a second idle signal lacking the idle state errors of the first idle signal. The first filter provides the second idle signal to receiver control logic that controls signal reception.

Abstract: Computer-readable media and methods for designing semiconductor artwork. Basic building blocks, or leaf cells, of an existing piece of semiconductor artwork are transferred to a new piece of semiconductor artwork in order to streamline the design process of the new design. In addition to being transferred, the position of METAL 1 layers within the leaf cells are also analyzed to avert possible design rule violations in the new design.

Abstract: Computer-readable media and methods for designing semiconductor artwork. Basic building blocks, or leaf cells, of an existing piece of semiconductor artwork are transferred to a new piece of semiconductor artwork in order to streamline the design process of the new design. In addition to being transferred, the position of METAL 1 layers within the leaf cells are also analyzed to avert possible design rule violations in the new design.