Abstract: Technology for a biometric identification system is described. The biometric identification system can include an infrared (IR) illumination device, a thermal imager, and a controller. The controller can determine, using a defined thermal profile, when a thermal image captured by the thermal imager includes a face of a user. The controller can determine, based on the thermal image, when the face of the user is located within a selected range of distances from the thermal imager. The controller can instruct the IR illumination device to illuminate for a selected period of time when the face of the user is located within the selected range of distances from the thermal imager.

Abstract: Manageability ports for inter-processor communication links, along with associated systems and methods, are generally provided.

Abstract: Manageability ports for inter-processor communication links, along with associated systems and methods, are generally provided.

Abstract: In some embodiments, a method for supporting multiple devices on a high speed physical link may be described. An embedded device may assert a link request pin to request to transmit data on a multi-point communications link that may serve a plurality of embedded devices. A controlling device may receive the link request signal. When the controlling device finishes sending data on the link, it may address the plurality of embedded devices in a round robin format and may determine which device asserted the link request pin. The embedded device that asserted the link request pin may send an acknowledgement signal to the controlling device when it is addressed.

Abstract: Manageability ports for inter-processor communication links, along with associated systems and methods, are generally provided.

Abstract: A wireless communication device to transmit and receive signals of two or more wireless networks is disclosed. The wireless communication device includes a first radio to transmit a first type of modulated signals in at least first and second frequency bands and a second radio to transmit a second type of modulated signals in at least third and forth frequency bands. The wireless communication device further includes a first front end module to transmit simultaneously the first and the third frequency bands of the first and second radio through two or more antennas utilizing multiple input multiple (MIMO) output transmission scheme and a second front end module to transmit simultaneously the second and the fourth frequency bands of the first and second radio through two or more antennas utilizing multiple input multiple (MIMO) output transmission scheme.

Abstract: Manageability ports for inter-processor communication links, along with associated systems and methods, are generally provided.

Abstract: In some embodiments, a method for supporting multiple devices on a high speed physical link may be described. An embedded device may assert a link request pin to request to transmit data on a multi-point communications link that may serve a plurality of embedded devices. A controlling device may receive the link request signal. When the controlling device finishes sending data on the link, it may address the plurality of embedded devices in a round robin format and may determine which device asserted the link request pin. The embedded device that asserted the link request pin may send an acknowledgement signal to the controlling device when it is addressed.

Abstract: A memory programmer may be coupled through a first processor and a physical interface to a semiconductor memory to be programmed. The interface may be the same interface that allows two separate processors in a multiprocessor memory to communicate with one another in one embodiment. Thus, an independent memory bus coupled directly to the memory components to be programmed may be eliminated, reducing form factor, decreasing costs, and increasing manufacturing throughput in some embodiments of the present invention.

Abstract: Method and apparatus relating to defining additional channels in an interprocessor communication system having broadcast and non-broadcast channels. A broadcast identifier may be sent on a channel defined to be non-broadcast, generating an additional broadcast channel outside the interprocessor communication protocol definition. Likewise a device-specific identifier may be sent on a channel defined to be a broadcast channel, generating an additional non-broadcast channel outside the interprocessor communication protocol definition.

Abstract: A wireless communication device to transmit and receive signals of two or more wireless networks is disclosed. The wireless communication device includes a first radio to transmit a first type of modulated signals in at least first and second frequency bands and a second radio to transmit a second type of modulated signals in at least third and forth frequency bands. The wireless communication device further includes a first front end module to transmit simultaneously the first and the third frequency bands of the first and second radio through two or more antennas utilizing multiple input multiple (MIMO) output transmission scheme and a second front end module to transmit simultaneously the second and the fourth frequency bands of the first and second radio through two or more antennas utilizing multiple input multiple (MIMO) output transmission scheme.

Abstract: A method of adjusting a power amplifier may include producing a power measure of an output signal of the power amplifier and estimating an estimated transmission error of the output signal from the power measure. The estimated transmission error may be compared with a maximum error that is associated with a data rate of the output signal. A bias voltage that is input to the power amplifier may be decreased if the comparing determines that the estimated transmission error is less than the maximum error.

Abstract: A memory programmer may be coupled through a first processor and a physical interface to a semiconductor memory to be programmed. The interface may be the same interface that allows two separate processors in a multiprocessor memory to communicate with one another in one embodiment. Thus, an independent memory bus coupled directly to the memory components to be programmed may be eliminated, reducing form factor, decreasing costs, and increasing manufacturing throughput in some embodiments of the present invention.

Abstract: Method and apparatus relating to an acknowledgement mechanism in an interconnected subsystem architecture. After a data message is transmitted, the transmitting device may transmit an acknowledge message on a channel undefined by the inter-subsystem communication protocol associated with the interconnection architecture. The undefined channel may be generated using a device-specific identifier on a channel defined to be a broadcast channel. The receiving device may acknowledge the transfer by switching a sideband control signal line.

Abstract: A memory programmer may be coupled through a first processor and a physical interface to a semiconductor memory to be programmed. The interface may be the same interface that allows two separate processors in a multiprocessor memory to communicate with one another in one embodiment. Thus, an independent memory bus coupled directly to the memory components to be programmed may be eliminated, reducing form factor, decreasing costs, and increasing manufacturing throughput in some embodiments of the present invention.