Abstract: A fully self-aligned polycrystalline silicon emitter bipolar transistor. Self-alignment of the p.sup.+ base contact (12) is achieved by using oxidized sidewalls (8) (sidewall spacers) of the emitter mesa (7) as part of the p.sup.+ base contact implantation mask. Collector contact (13) alignment can be achieved using oxidized sidewalls (17) of polycrystalline silicon alignment mesas (14) defined in the same polysilicon as the emitter mesa (7) but deposited on oxide (2) rather than the implanted base region (5).

Abstract: A process for fabricating a CMOS compatible bipolar transistor is described. The transistor, which is of the polysilicon emitter type, is fabricated by forming a p-type layer in a well, providing a polysilicon emitter in contact with the layer, using the emitter as a mask to implant p.sup.+ -type base contact regions, and applying contacts to the device.

Abstract: A fully self-aligned polycrystalline silicon emitter bipolar transistor. Self-alignment of the p.sup.+ base contact (12) is achieved by using oxidised sidewalls (8) (sidewall spacers) of the emitter mesa (7) as part of the p.sup.+ base contact implantation mask. Collector contact (13) alignment can be achieved using oxidised sidewalls (17) of polycrystalline silicon alignment mesas (14) defined in the same polysilicon as the emitter mesa (7) but deposited on oxide (2) rather than the implanted base region (5).

Abstract: A bipolar transistor structure (1) which can be used in an integrated circuit where bipolar (1) and CMOS transistors (2,3) are formed simultaneously on one substrate. In integrated circuit form the material, for example polycrystalline silicon, used for the gates (11,21) of the CMOS transistors is also used for the emitters (29) of the bipolar transistors, the collectors of the bipolar devices are comprised by doped wells (5) in the substrate (4) and the base contacts of the bipolar devices are comprised by regions (27,27a) equivalent to source and drain regions (17,18) of the n-well MOS transistors and bridged by base implants (28). The conventional CMOS processing is modified by the addition of two masking steps and one implant (base implant).

Abstract: A method of manufacturing a bipolar transistor (1) with semi-self-aligned p.sup.+ base contacts (27,27a). A p-type base region (28) is formed in a surface region of an n-type region 5 comprising a collector. An element (29) of, for example, n.sup.+ doped polycrystalline silicon, and comprising an emitter, is formed on the surface in contact with the base region (28). The base contacts (27,27a) are formed by implantation and using the element (29) as a mask. An n.sup.+ collector contact (25) is made to the n-tpe region (5).

Abstract: A bipolar transistor structure (1) which can be used in an integrated circuit where bipolar (1) and CMOS transistors (2,3) are formed simultaneously on one substrate. In integrated circuit form the material, for example polycrystalline silicon, used for the gates (11,21) of the CMOS transistors is also used for the emitters (29) of the bipolar transistors, the collectors of the bipolar devices are comprised by doped wells (5) in the substrate (4) and the base contacts of the bipolar devices are comprised by regions (27,27a) equivalent to source and drain regions (17,18) of the n-well MOS transistors and bridged by base implants (28). The conventional CMOS processing is modified by the addition of two masking steps and one implant (base implant).

Abstract: In order to prevent diffusion of silicon from under a titanium disilicide interconnect (1) and into an overlying aluminium layer (6), the disilicide is selectively nitrided by annealing in nitrogen at the points where interconnection between the disilicide and aluminium is required via holes (4) in a silicon dioxide layer (3). The titanium nitrode contacts (5) thus formed in a truly self-aligned manner provide a good barrier to silicon diffusion while having an acceptable low resistivity.

Abstract: In making bipolar transistors, an interfacial oxide layer (5) is formed over ther monocrystalline region (1), and polysilicon (6) is formed both thereon as an extrinsic emitter region. After doping the polysilicon a monocrystalline emitter region (4) is produced in the base region by diffusion from the extrinsic polysilicon emitter region. The oxide layer (5) acts as a diffusion barrier to ensure that excessive dopant does not reach the monocrystalline region.After the above operation, a thermal treatment is effected at a higher temperature, e.g. 1100.degree. C., for a few seconds, which breaks down the interfacial oxide layer referred to above. This temporary use of the interfacial oxide layer leads to better and more consistant transistor characteristics.

Abstract: A fully self-aligned polycrystalline silicon emitter bipolar transistor. Self-alignment of the p.sup.+ base contact (12) is achieved by using oxidized sidewalls (8) (sidewall spacers) of the emitter mesa (7) as part of the p.sup.+ base contact implantation mask. Collector contact (13) alignment can be achieved using oxidized sidewalls (17) of polycrystalline silicon alignment mesas (14) defined in the same polysilicon as the emitter mesa (7) but deposited on oxide (2) rather than the implanted base region (5).

Abstract: Dopants in semiconductor bodies which have been deactivated during processing are reactivated by pulse heating the body to a temperature within the region in which the semiconductor sheet resistivity decreases with increasing anneal temperature. Typically this comprises raising the body to 1000.degree. C. within 40 seconds or less in an inert atmosphere and allowing it to cool immediately or within approximately 30 seconds. The heating is so rapid that diffusion side effects are minimized. Pulse heating may be achieved by means of a sealable microwave heating chamber (1) which can be pressurized or vented as desired and into which microwave energy is directed for a predetermined time. The microwave heating can also be employed for other processing, particularly high pressure oxidation of silicon.

Abstract: Polysilicon elements of integrated circuits, for example gates (24) or interconnects, are provided with metallic silicide layers (26) in order to take advantage of the lower resistivity thereof. The polysilicon elements are defined on an oxide layer (23) disposed on a silicon substrate (20) before polysilicon metallization. After polysilicon metallization the metal and polysilicon are caused to interdiffuse to form silicide layers (26) covering the polysilicon elements (24).

Abstract: Dopants in semiconductor bodies which have been deactivated during processing are reactivated by pulse heating the body to a temperature within the region in which the semiconductor sheet resistivity decreases with increasing anneal temperature. Typically this comprises raising the body to 1000.degree. C. within 40 seconds or less in an inert atmosphere and allowing it to cool immediately or within approximately 30 seconds. The heating is so rapid that diffusion side effects are minimized. Pulse heating may be achieved by means of a sealable microwave heating chamber (1) which can be pressurized or vented as desired and into which microwave energy is directed for a predetermined time. The microwave heating can also be employed for other processing, particularly high pressure oxidation of silicon.

Abstract: A process for isolating a semiconductor device formed in a p-type silicon substrate includes implanting a layer of oxygen ions below the device. The substrate is then heated to 430.degree.-470.degree. C. to activate the silicon/oxygen complexes thus formed and compensate or overcompensate the region thus forming an intrinsic or n-type isolating layer. The technique may be employed for the isolation of DMOS structures.

Abstract: A metallic silicide layer is formed on a substrate by pulse heating, in an inert atmosphere, metal and silicon deposited on the substrate to a temperature and for a time sufficient to cause interdiffusion of the metal and silicon.

Abstract: A process for annealing crystal damage in ion implanted semiconductor devices in which the device is rapidly heated to a temperature between 450.degree. and 900.degree. C. and allowed to cool. It has been found that such heating of the device to these relatively low temperatures results in rapid annealing. In one application the device (17) may be heated on a graphite element (14) mounted between electrodes (15) in an inert atmosphere in a chamber (11). The process may be enhanced by the application of optical radiation from a Xenon lamp (19).