Abstract: An audio signal processor for processing 1-bit signals, comprises an input 40 for receiving a 1-bit signal, means 41, 42 for applying a predetermined filter characteristic to the 1-bit signal whereby the signal is also converted to an n-bit signal where n is greater than one, means 43 for determining the absolute value of the n-bit signal, means 46, 51 for producing a dynamics control signal dependent on the said absolute value, means 48 for applying the dynamics control signal to the 1-bit input signal, and means 49 for requantizing the dynamics controlled signal as a 1-bit signal and shaping the noise in the requantised 1-bit signal. Circuits for producing LOG base 2 and the corresponding anti-log are also disclosed.

Abstract: A 1-bit nth order Delta Sigma Modulator where n is at least one comprises a linear signal processing section (50) which processes the 1-bit signal and produces a p bit output, a filter (52) which filters the p bit signal, an adder (53) a quantizer Q coupled to the output of the adder (53) to quantize a p bit signal to a 1-bit output signal, and a noise shaping section 51 which feeds the 1-bit output signal back to the adder 53.

Abstract: Audio processing apparatus comprises an audio processor operable to apply one or more processing operations from a set of audio processing operations to an input audio signal; adjustment controls for adjusting processing parameters associated with each of the set of processing operations; a display screen for displaying icons representing each processing operation of the set of audio processing operations; and a detector for detecting user operation of the adjustment controls associated with an a processing operation and, in response to such a detection, for displacing the display position of the icon associated with that processing operation.

Abstract: A 1-bit signal processor receives a 1-bit signal having a first sampling rate eg 64 fs. An upconverter (41) increases the sampling rate to eg 128 fs. A series of Delta Sigma Modulators (42, 43) processes the signal. The processed signal is down-converted by a converter (44) to 64 fs. As least the Delta Sigma Modulators may be implemented on an integrated circuit. The down-converter is arranged to prevent noise being folded back into the signal band.

Abstract: A signal processor for 1-bit signals comprises an nth order D Sigma Modulator (DSM) having an input (4) for receiving a 1-bit signal and an output (5) at which a processed 1-bit signal is produced by a quantizer (Q). The quantizer (Q) receives a p-bit signal from a series of 5 signal integration stages. Each stage comprises a first 1-bit multiplier (An) coupled to the input (4), a second 1-bit multiplier (Cn) coupled to the output (5), an adder (6n) which sums the outputs of the coefficient multipliers and an integrator (7n) which integrates the output of the adder (6n). A final stage comprises a coefficient multiplier (An+1) and an adder (6n+1). The adder (6n+1) sums the output of the coefficient multiplier (An+1) and the output of the integrator of the preceding integration stage. The input signal is fed to all the stages except the final stage via a 1-bit delay. The output signal of the quantizer is fed back to the stages via a 1-bit delay.

Abstract: One-bit digital signal processing apparatus for generating an output one-bit signal by switching from a first to a second one-bit signal in response to a detection that m consecutive bits of the first and second signal are identical, the apparatus comprising means for varying m in dependence on the urgency of the switching operation.

Abstract: A signal processor for processing 1-bit signals comprising at least a pair of Delta Sigma Modulators (DSM) coupled in series, one of the said pair of DSMs having an signal-band noise-shaping filter characteristic complementary to the signal-band noise-shaping filter characteristic of the other of the pair of DSMs.

Abstract: A signal processor for 1-bit signals comprises a nth order Delta-Sigma Modulator, where n is greater than or equal to 2. The Delta-Sigma Modulator comprises a first input 4A for receiving a first 1-bit signal and a second input 4B for receiving a second 1-bit signal. A quantizer Q quantises a p bit signal to 1-bit form, the requantized signal being the output signal of the processor. A plurality of signal combiners are provided. A first combiner (A1, 61, c1 b1, 71) forms the integral of the sum of the input signals and the output signal multiplied by coefficients A1, B1 and C1. At least one intermediate combiner forms the integral of the sum of the first and second input signals and the output signal multiplied by coefficients A2, B2, C2 together with the output of the first combiner. The final combiner a4, b4, 64 forms the integral of the sum of the first and second signals multiplied by coefficients A4 and B4 together with the output of the preceding intermediate combiner.

Abstract: A 1-bit signal (44) is compressed (40, 41) by dividing it into a series of n-bit words and encoding the words according to the probability of their occurrence.

Abstract: An nth order Delta Sigma Modulator (DSM) where n.gtoreq.

Abstract: A 1-bit signal processor receives a 1-bit signal having a first sampling rate eg 64 fs. An upconverter (41) increases the sampling rate to eg 128 fs. A series of Delta Sigma Modulators (42, 43) processes the signal. The processed signal is down-converted by a converter (44) to 64 fs. As least the Delta Sigma Modulators may be implemented on an integrated circuit. The down-converter is arranged to prevent noise being folded back into the signal band.

Abstract: An input stage for receiving an input signal having a signal level varying to represent successive states of a one-bit digital signal, comprises: a thresholder for detecting whether the input signal level is above or below a threshold signal level; in which: the input of the thresholder is biased with a bias signal varying between a signal level above the threshold signal level and a signal level below the threshold signal level; and the amplitude of the alternating component of the bias signal is lower than the amplitude of the alternating component of the input signal.

Abstract: An arithmetic stage calculates the sum AX+BY where A and B are 1-bit signals and X and Y p bit coefficients X=7 and Y=3 and the corresponding bits b.sub.1 to b.sub.5 are represented together with the corresponding logical states of A and B. It will be seen that for example column b.sub.3 together with columns A and B is the truth table of an NAND gate. Column b.sub.2 together with columns A and B is the truth table of a COINCIDENCE gate.In the example of FIG. 5 column b.sub.4 equals B; column b.sub.1 is logical 0 whatever the states of A and B; and column b.sub.5 is NOT A.Thus in accordance with one illustrative embodiment of the invention the arithmetic stage 40 may be implemented by the logic circuit of FIG. 6 wherebit b.sub.5 is produced by inverting A,bit b.sub.4 is produced by coupling output b.sub.1 to input B, via a direct connection 60,bit b.sub.3 is produced by a NAND gate 61,bit b.sub.2 is produced by a COINCIDENCE gate 62, andbit b.sub.1 is produced by coupling output b.sub.

Abstract: A loudspeaker comprises a yoke; one or more vibration driving coils disposed so as to interact magnetically with the yoke when an electrical current flows through the coils; and one or more signal amplifying devices mounted on or near the yoke, the amplifying devices being operable to receive an input audio signal, to amplify the input signal to generate an amplified signal, and to supply the amplified signal to the vibration driving coils.