Abstract: Transaction code written by the programmer may be translated, replaced or transformed into a code that is configured to implement transactions according to any of various techniques. A compiler may replace programmer written transaction code into code allowing multiple compatible transaction implementation techniques to be used in the same program, and at the same time. A programmer may write transaction code once using familiar coding styles, but the transaction to be effected according to one of a number of compatible alternative implementation techniques. The compiler may enable the implementation of multiple, alternative transactional memory schemes. The particular technique implemented for each transaction may not be decided until runtime. At runtime, any of the various implemented techniques may be used to effect the transaction and if a first technique fails or is inappropriate for a particular transaction, one or more other techniques may be attempted.

Abstract: A processor includes a set of registers implemented internal to the processor and plural virtual registers. The set of registers are each individually addressable using a corresponding register identification and the plural virtual registers are each individually addressable using a corresponding virtual register identification. At least one of the virtual registers is an auxiliary register implemented internal to the processor. The processor transfers values between the set of registers and the plural virtual registers under control of a transfer operation.

Abstract: This invention is an apparatus, method, and system for translational lookaside buffer coherency in computer systems having a plurality of processors, each having an associated TLB for storing address translation data, and the computer system having a plurality of independent paths upon which the plurality of processors are distributed and a TLB message transmitted on said plurality of independent paths.

Abstract: A method and apparatus for altering code to effectively hide main memory latency using software prefetching with non-faulting loads prefetches data from main memory into local cache memory at some point prior to the time when the data is requested by the CPU during code execution. The CPU then retrieves its requested data from local cache instead of directly seeing the memory latency. The non-faulting loads allow for safety and more flexibility in executing the prefetch operation earlier because they alleviate the concern of incurring a segmentation fault, particularly when dealing with linked data structures. Accordingly, the memory access latency that the CPU sees is essentially the cache memory access latency. Since this latency is much less than the memory latency resulting from a cache miss, the overall system performance is improved.

Abstract: This invention provides for filtering instructions to obtain more precise event counts with a plurality of instructions having a counter enable bit, executing the instructions thereby causing a plurality of events, filtering the instructions, activating the counter enable bit if the instructions fall within the filter, which then determines whether an event counter coupled to the event is incremented.