Abstract: The present invention is directed to the synchronization of clock frequencies across packet data networks. In particular, one or more communication endpoints may produce a clock signal that is synchronized to a master clock source. Synchronization is performed by providing timing packets containing information regarding a number of clock cycles counted on the master clock source to a controlled clock source. The controlled clock source uses the provided count to increment a counter value. At the same time, the counter value on the controlled clock source is decremented by the controlled clock source clock. The resulting counter value is used to address a correction table. A correction value from the correction table is applied to the frequency control input of the controlled clock source clock.

Abstract: A communication circuitry for providing effective detection of tones in a communication network. The communication circuitry comprises filtration circuitry, summation circuitry, detection circuitry, and interface circuitry. The filtration circuitry is coupled to the summation circuitry and is configured to receive a communication, process the communication to estimate an echo return in the communication, and provide the estimated echo return to the summation circuitry. The summation circuitry is coupled to the detection circuitry and configured to receive the estimated echo return from the filtration circuitry, receive a tone transmission and echo return from the interface circuitry, subtract the estimated echo return from the tone transmission to generate a substantially pure tone, and provide the substantially pure tone to the detection circuitry. The detection circuitry is configured to receive the substantially pure tone and process the substantially pure tone to perform a programmed operation.