Abstract: Apparatus and methods for nonlinearity cancellation in electronic systems are disclosed. In certain embodiments, an electronic system includes two or more circuit channels that process a common input signal in parallel and that each include at least one instantiation of a circuit that behaves nonlinearly. Thus, the nonlinear circuit is replicated and included at least once in each circuit channel. Each of the circuit channels has an input scaling factor and an output scaling factor that can vary from one circuit channel to another. The output signals from the circuit channels after scaling are combined to generate a combined output signal. The input and output scaling factors are selected to cancel or reduce nonlinearities.

Abstract: One embodiment is a reconfigurable mixer topology for selectively implementing one of a harmonic rejection mixer (HRM) and a subharmonic mixer (SHM), the reconfigurable mixer topology comprising a mixer core comprising a plurality of differential mixers each having a first clock input and a second clock input; a clock generator for generating a plurality of clock signals each having a different phase; and a clock distributor for distributing the plurality of clock signals to the first and second clock inputs of the differential mixers in accordance with a designated operation of the reconfigurable mixer as an HRM or an SHM.

Abstract: Herein disclosed are systems and circuitry for protecting against overdrive and electrostatic discharge. For example, protection circuitry may include field effect transistors to discharge overdrive outside of an operational voltage range of a circuit in some embodiments to prevent damage to the circuit. Further, the protection circuitry may utilize diode features inherent in the field effect transistors to protect against electrostatic discharge in some embodiments. The circuitry may be implemented in radio frequency sampling analog-to-digital converters and can provide for single-ended signal input and/or output for the analog-to-digital converters.

Abstract: One embodiment is a reconfigurable mixer topology for selectively implementing one of a harmonic rejection mixer (HRM) and a subharmonic mixer (SHM), the reconfigurable mixer topology comprising a mixer core comprising a plurality of differential mixers each having a first clock input and a second clock input; a clock generator for generating a plurality of clock signals each having a different phase; and a clock distributor for distributing the plurality of clock signals to the first and second clock inputs of the differential mixers in accordance with a designated operation of the reconfigurable mixer as an HRM or an SHM.

Abstract: Herein disclosed are systems and circuitry for protecting against overdrive and electrostatic discharge. For example, protection circuitry may include field effect transistors to discharge overdrive outside of an operational voltage range of a circuit in some embodiments to prevent damage to the circuit. Further, the protection circuitry may utilize diode features inherent in the field effect transistors to protect against electrostatic discharge in some embodiments. The circuitry may be implemented in radio frequency sampling analog-to-digital converters and can provide for single-ended signal input and/or output for the analog-to-digital converters.

Abstract: Various approaches to implementing digital loopback in a radio frequency (RF) system are disclosed. An example RF system includes a receiver that includes an ADC and a transmitter that includes a DAC. The apparatus includes multiple digital loopback circuits provided at different points between the digital domain processing of the receiver and the transmitter. Each digital loopback circuit may include a combiner and one or more weighing circuits, which make the circuit programmable. The combiner of a given digital loopback circuit is configured to combine a RX signal and a TX signal at a particular point of the digital domain processing of the receiver and the transmitter where said digital loopback circuit is implemented. The one or more weighting circuits are configured to define the how much of the TX signal and/or RX signal is used for said combination.

Abstract: An ultra-wideband distributed ADC can be cascaded to build high performance radio frequency (RF) analog electronics integrated with advanced digital complementary metal-oxide-semiconductor (CMOS) electronics on the same wafer. Advantages can include wide spectral coverage, high resolution, large dynamic range, and high information processing bandwidth. Part of an overall system includes a precise, programmable, real-time delay circuit that can achieve picosecond accuracy.

Abstract: Improved track and hold (T/H) circuits can help analog-to-digital converters (ADCs) achieve higher performance and lower power consumption. The improved T/H circuits can drive high speed and interleaved ADCs, and the design of the circuits enable additive and multiplicative pseudo-random dither signals to be injected in the T/H circuits. The dither signals can be used to calibrate (e.g., linearize) the T/H circuits and the ADC(s). In addition, the dither signal can be used to dither any remaining non-linearity, and to calibrate offset/gain mismatches in interleaved ADCs. The T/H circuit design also can integrate an amplifier in the T/H circuit, which can be used to improve the signal-to-noise ratio (SNR) of the ADC or to act as a variable gain amplifier (VGA) in front of the ADC.

Abstract: An ultra-wideband distributed ADC can be cascaded to build high performance radio frequency (RF) analog electronics integrated with advanced digital complementary metal-oxide-semiconductor (CMOS) electronics on the same wafer. Advantages can include wide spectral coverage, high resolution, large dynamic range, and high information processing bandwidth. Part of an overall system includes a precise, programmable, real-time delay circuit that can achieve picosecond accuracy.

Abstract: Improved track and hold (T/H) circuits can help analog-to-digital converters (ADCs) achieve higher performance and lower power consumption. The improved T/H circuits can drive high speed and interleaved ADCs, and the design of the circuits enable additive and multiplicative pseudo-random dither signals to be injected in the T/H circuits. The dither signals can be used to calibrate (e.g., linearize) the T/H circuits and the ADC(s). In addition, the dither signal can be used to dither any remaining non-linearity, and to calibrate offset/gain mismatches in interleaved ADCs. The T/H circuit design also can integrate an amplifier in the T/H circuit, which can be used to improve the signal-to-noise ratio (SNR) of the ADC or to act as a variable gain amplifier (VGA) in front of the ADC.