Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: An electrical connector including a first and second assembly that are matable with one another by a sliding push fit to establish electrical interconnection between the two assemblies is disclosed. The first assembly includes a contact pin with a collar extending concentrically around the pin to define a recess therebetween, with the collar supporting on its inner surface a first resilient contact element. The second assembly includes a sleeve open at one end thereof such that the sleeve can be received in the recess of the first assembly, with the sleeve supporting on its inner surface a second resilient contact element. The two assemblies may be arranged such that, when the second assembly is inserted into the first assembly, the first resilient contact element makes sliding electrical contact with an external surface of the sleeve of the second assembly, and the second resilient contact element makes sliding electrical contact with the external surface of the pin of the first assembly.

Abstract: An electrical connector including a first and second assembly that are matable with one another by a sliding push fit to establish electrical interconnection between the two assemblies is disclosed. The first assembly includes a contact pin with a collar extending concentrically around the pin to define a recess therebetween, with the collar supporting on its inner surface a first resilient contact element. The second assembly includes a sleeve open at one end thereof such that the sleeve can be received in the recess of the first assembly, with the sleeve supporting on its inner surface a second resilient contact element. The two assemblies may be arranged such that, when the second assembly is inserted into the first assembly, the first resilient contact element makes sliding electrical contact with an external surface of the sleeve of the second assembly, and the second resilient contact element makes sliding electrical contact with the external surface of the pin of the first assembly.

Abstract: The parity of this invention includes two arrays of parities surrounding the memory. One array is generated in parallel. The other array is generated in serial. The two dimensional parity is used to protect, locate and correct errors automatically. The second parity is provided for only a subset of the address range of the memory. The memory controller does not compare the second parities unless there is a soft error in the first parity. The second parities are calculated upon command and not upon each memory write as the first parity.

Abstract: An electrical connector for high current applications has a mating plug and socket assembly. The socket assembly has two sockets arranged coaxially of one another and electrically interconnected. The central socket receives and contacts a pin on the plug assembly; the other socket contacts the external surface of a tubular sleeve surrounding and integrally electrically connected with the pin. The socket assembly also has a third socket electrically insulated from and arranged coaxially outwardly of the other two sockets. The third socket makes electrical contact with the outer surface of a tubular contact extending coaxially of the pin and electrically insulated from it. The sockets each have a hyperboloid configuration of multiple resilient wires to make contact with the pin, sleeve and outer contact.

Abstract: A memory system or a digital signal processor (DSP) includes single-bit-error detection hardware in its level two (L2) memory controller to mitigate the effects of soft errors. Error detection hardware detects erroneous data that is fetched by the central processing unit and signals the central processing unit. The parity is generated and checked only for whole memory line accesses. This technique is especially useful for cache memory. The central processing unit can query the memory controller as to the specific location that generated the error and decide the next course of action based on the type of data affected.

Abstract: An optical connector assembly has several optical and electrical connectors mounted in mateable rectangular housings. Each optical connector is resiliently mounted in an alignment sleeve by means of a spring clip encircling the connector and contacting the sleeve. The alignment sleeves are themselves resiliently mounted in passages through the housings by spring clips encircling the sleeves and contacting passages within which the sleeves are mounted.

Abstract: An electrical connector for high current applications has a mating plug and socket assembly. The socket assembly has two sockets arranged coaxially of one another and electrically interconnected. The central socket receives and contacts a pin on the plug assembly; the other socket contacts the external surface of a tubular sleeve surrounding and integrally electrically connected with the pin. The socket assembly also has a third socket electrically insulated from and arranged coaxially outwardly of the other two sockets. The third socket makes electrical contact with the outer surface of a tubular contact extending coaxially of the pin and electrically insulated from it. The sockets each have a hyperboloid configuration of multiple resilient wires to make contact with the pin, sleeve and outer contact.

Abstract: An optical connector assembly has several optical and electrical connectors mounted in mateable rectangular housings. Each optical connector is resiliently mounted in an alignment sleeve by means of a spring clip encircling the connector and contacting the sleeve. The alignment sleeves are themselves resiliently mounted in passages through the housings by spring clips encircling the sleeves and contacting passages within which the sleeves are mounted.

Abstract: The parity of this invention includes two arrays of parities surrounding the memory. One array is generated in parallel. The other array is generated in serial. The two dimensional parity is used to protect, locate and correct errors automatically. The second parity is provided for only a subset of the address range of the memory. The memory controller does not compare the second parities unless there is a soft error in the first parity. The second parities are calculated upon command and not upon each memory write as the first parity.

Abstract: A memory system or a digital signal processor (DSP) includes single-bit-error detection hardware in its level two (L2) memory controller to mitigate the effects of soft errors. Error detection hardware detects erroneous data that is fetched by the central processing unit and signals the central processing unit. The parity is generated and checked only for whole memory line accesses. This technique is especially useful for cache memory. The central processing unit can query the memory controller as to the specific location that generated the error and decide the next course of action based on the type of data affected.

Abstract: An avionics housing has electrical connectors mounted centrally on a front face. Transient voltage suppressors are located in an array of holes in a metal plate to each side of the connectors, beneath removable panels so that they are accessible on the front face after removal of the panels. The suppressors extend through the plate to connect with circuit boards on the opposite side that have tracks connecting with the connectors. A filter module is secured behind the circuit boards and supports filters that connect with connections on the boards. A rear connection assembly carries connectors on its rear surface by which connection is made to circuits within the unit. Flexi-rigid circuits interconnect the rear connectors with socket array boards on the front of the rear connection assembly and these, in turn, connect with contacts on the filter module.

Abstract: An electrical connector has a forward assembly with an outer metal housing supporting several insulative blocks containing the connector contacts. The rear end of each contact has a socket into which is inserted the forward end of conductors contained in a rear assembly. Some of the conductors are filtered and others unfiltered. Connection is made to the rear end of the conductors in the rear assembly by means of plates connected at the end of a cable, the plates supporting contacts that are a push-fit in the rear of the conductors in the rear assembly.