Patents by Inventor Peter Dibble

Peter Dibble has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7171501
    Abstract: An invention is provided for a synchronous transfer of control. An asynchronous interrupt exception is received, and in response, the value of a reference counter is determined. The value of the reference counter is based on the execution of synchronized code. Generally, the reference counter is initialized to a predetermined number, and altered based on the execution of synchronized code. When the asynchronous interrupt exception is received, the method is asynchronously interrupted when the value of the reference counter is equal to the predetermined number.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: January 30, 2007
    Assignee: Sun Microsystems, Inc.
    Inventors: Gregory Bollella, Benjamin M. Brosgol, Scott D. Robbins, David S. Hardin, Peter Dibble
  • Publication number: 20030140086
    Abstract: An invention is provided for asynchronous transfer of control. An asynchronous interrupt exception is received, and in response, the value of a reference counter is determined. The value of the reference counter is based on the execution of synchronized code. Generally, the reference counter is initialized to a predetermined number, and altered based on the execution of synchronized code. When the asynchronous interrupt exception is received, the method is asynchronously interrupted when the value of the reference counter is equal to the predetermined number.
    Type: Application
    Filed: October 23, 2002
    Publication date: July 24, 2003
    Applicant: Sun Microsystems, Inc.
    Inventors: Gregory Bollella, Benjamin M. Brosgol, Scott D. Robbins, David S. Hardin, Peter Dibble
  • Publication number: 20030097537
    Abstract: An invention is provided for managing memory that includes a heap memory and scoped memory. The scoped memory is managed separately from the heap memory, and includes defining a scope tree structure having a root node and a plurality of child nodes. The child nodes are capable of having respective child nodes, however each child node has only one parent node. Each child node corresponds to a scoped memory space that forms a logical memory pool corresponding to a particular scoped memory. During memory management, a thread is allowed to enter a particular child node only through the parent node of the particular child node. In this manner, a thread executing in a particular scooped memory space allocates memory from the scoped memory corresponding to the particular scoped memory space.
    Type: Application
    Filed: October 23, 2002
    Publication date: May 22, 2003
    Applicant: Sun Microsystems, Inc.
    Inventors: Gregory Bollella, Scott D. Robbins, David S. Hardin, Benjamin M. Brosgol, Peter Dibble, Pratik Solanki