Abstract: A test circuit for use in an MOS device includes two inputs, a first input which is responsive to a test signal of opposite polarity to that of the supply voltage, and a second input which is responsive to a test signal of the same polarity as that of the supply voltage but of a substantially higher magnitude than that of the supply voltage. The test circuit is enabled only when both the opposite polarity signal on the first input and the higher magnitude signal on the second input occur. In this manner a substantial immunity to spurious voltage transients of either polarity is obtained while permitting the test circuit and the circuits on the same MOS device being tested to share common terminals.