Abstract: A distributed architecture for driving various electro-optic reflective display devices (620) is disclosed. Analog processors (6-15) are positioned in close proximity to the electro-optic reflective segments (650) being driven while digital processing functions are performed at a remote location. The analog and digital processors communicate via a bus (640). Various bus types and architectures for coupling the analog and digital processors are disclosed. The distributed architecture is particularly useful in electrochromic displays where the inherent properties of the display require analog sensing of each segment.

Abstract: A wireless transmit receive unit (WTRU) recovers data from a plurality of data signals received as a received vector. The WTRU determines data of the received vector by determining a Cholesky factor of an N by N matrix and using the determined Cholesky factor in forward and backward substitution to determine data of the received data signals. The WTRU comprises an array of at most N scalar processing elements. The array has input for receiving elements from the N by N matrix and the received vector. Each scalar processing element is used in determining the Cholesky factor and performs forward and backward substitution. The array outputs data of the received vector.

Abstract: A user equipment or base station recovers data from a plurality of data signals received as a received vector. The user equipment determines data of the received vector by determining a Cholesky factor of an N by N matrix and using the determined Cholesky factor in forward and backward substitution to determine data of the received data signals. The user equipment or base station comprises an array of at most N scalar processing elements. The array has input for receiving elements from the N by N matrix and the received vector. Each scalar processing element is used in determining the Cholesky factor and performs forward and backward substitution. The array outputs data of the received vector.

Abstract: A circuit is capable of performing a complex division and dual complex multiplication. The complex division involves dividing a first complex value by a second complex value and the dual complex multiplication involves multiplying a third complex value by a fourth complex value and a fifth complex value by a sixth complex value. The circuit comprises a first input configured to receive the first and second complex values when the circuit is performing the complex division and the third and fourth complex values when the circuit is performing the dual complex multiplication. A second input is configured to receive the second complex value when performing the complex division and the fifth and sixth complex values when performing dual complex multiplication. A first output produces a result of complex multiplication of the third and fourth complex values when the circuit is performing the dual complex multiplication.

Abstract: A circuit is capable of performing a complex division and dual complex multiplication. The complex division involves dividing a first complex value by a second complex value and the dual complex multiplication involves multiplying a third complex value by a fourth complex value and a fifth complex value by a sixth complex value. The circuit comprises a first input configured to receive the first and second complex values when the circuit is performing the complex division and the third and fourth complex values when the circuit is performing the dual complex multiplication. A second input is configured to receive the second complex value when performing the complex division and the fifth and sixth complex values when performing dual complex multiplication. A first output produces a result of complex multiplication of the third and fourth complex values when the circuit is performing the dual complex multiplication.

Abstract: A circuit performs complex division and dual complex multiplication. The circuit has a plurality of multipliers. Each of the plurality of multipliers is used in both the complex division and the dual complex multiplications. The circuit also has a plurality of components capable of adding and subtracting. Each adding and subtracting component is used during the complex division and the dual complex multiplication and switches between operation as an adder and a subtractor between performing the complex division and the dual complex multiplication. Preferred potential uses for the circuit are in a receiver of a user equipment or a base station. The circuit is used in a fast Fourier transform (FFT) based channel estimation or a FFT based data detection.

Abstract: A circuit performs complex division and dual complex multiplication. The circuit has a plurality of multipliers. Each of the plurality of multipliers is used in both the complex division and the dual complex multiplications. The circuit also has a plurality of components capable of adding and subtracting. Each adding and subtracting component is used during the complex division and the dual complex multiplication and switches between operation as an adder and a subtractor between performing the complex division and the dual complex multiplication. Preferred potential uses for the circuit are in a receiver of a user equipment or a base station. The circuit is used in a fast Fourier transform (FFT) based channel estimation or a FFT based data detection.

Abstract: A user equipment or base station recovers data from a plurality of data signals received as a received vector. The user equipment determines data of the received vector by determining a Cholesky factor of an N by N matrix and using the determined Cholesky factor in forward and backward substitution to determine data of the received data signals. The user equipment or base station comprises an array of at most N scalar processing elements. The array has input for receiving elements from the N by N matrix and the received vector. Each scalar processing element is used in determining the Cholesky factor and performs forward and backward substitution. The array outputs data of the received vector.