Abstract: What is provided is a system and method for reducing the storage requirements for delay networks used in performing timing analysis. A circuit delay network is transformed by processing all the possible hubs of the input pairs which are created from a bipartite delay graph of the circuit. A smaller delay network is formed by iteratively selecting the hub with the largest edge-saving and removing the conflicts from the remaining unselected hubs. The selections continues until there are no longer any unselected hubs. Further processing can occur using the selected hubs as inputs to insure that there are no further layers of hubs. The composite of all selected hubs and any inputs and outputs that do not contained hubs is an abstracted delay model for the circuit which can be efficiently stored. These models are subsequently used to reduce the computational requirements for timing analysis performed on delay networks at a higher level.