Abstract: An array of interconnected node units for data handling, processing or data storage may be formed as an integrated circuit on a semiconductor wafer or as separate elements of a fault-tolerant computer. Each node unit includes a controlled switch for routing signal packets to destination node units whose addresses are included in the packets. Some node units include a data processor and/or memory together with a packet generator and a packet receiver. The controller of a switch stores details of which adjacent node units are not working and directs signal packets on paths round the non-working node units. The signal packets include a handedness bit to indicate to which side of a non-working node unit they are to be directed. The handedness bit is changed by node units at the edge of the array.