Abstract: Multi-link selection based on Transmit Power Control (TPC) may be provided. A computing device may receive Multi-Link Device (MLD) association information associated with a client device. The MLD association information may describe MLD links the client device may require. A set of MLD links available on a network may be determined based on the MLD association information. The determined set of MLD links may then be sent to the client device.

Abstract: Multi-link selection based on Transmit Power Control (TPC) may be provided. A computing device may receive Multi-Link Device (MLD) association information associated with a client device. The MLD association information may describe MLD links the client device may require. A set of MLD links available on a network may be determined based on the MLD association information. The determined set of MLD links may then be sent to the client device.

Abstract: A network controller, which allows data frames received to be held in an internal memory buffer, has the capability to selectively switch between a DMA mode of data transfer and a non-DMA mode of data transfer to move data frames from the internal memory buffer to a desired location. When the overflow of the memory buffer is anticipated, a DMA controller is automatically engaged to move the data frames to a system memory to prevent the received frames from being discarded. An auto-DMA decision logic engages the DMA controller based on factors such as the number of data frames accumulated in the memory buffer, remaining capacity of the memory buffer, frame loading and unloading rates, and time interval during which data frames have been received without completely unloading the memory buffer.

Abstract: In an interrupt-driven data frame stream receiver, an interrupt to a host processor is applied by an interrupt system that comprises a timer logic circuit, an address match circuit, a data frame counter, a cyclic redundancy check (CRC) logic circuit, a frame length logic circuit, and a frame content detector. Each of these circuits is coupled to an OR gate. A Start Frame Delimiter (SFD) detector is connected to the inputs of the other circuits.

Abstract: A network controller, which allows data frames received to be held in an internal memory buffer, has the capability to selectively switch between a DMA mode of data transfer and a non-DMA mode of data transfer to move data frames from the internal memory buffer to a desired location. When the overflow of the memory buffer is anticipated, a DMA controller is automatically engaged to move the data frames to a system memory to prevent the received frames from being discarded. An auto-DMA decision logic engages the DMA controller based on factors such as the number of data frames accumulated in the memory buffer, remaining capacity of the memory buffer, frame loading and unloading rates, and time interval during which data frames have been received without completely unloading the memory buffer.

Abstract: A method and arrangement for receiving data in a direct memory access (DMA) controller and storing the received data in a host memory in a computer system determines the size of the packets of data to be transferred. The host memory is subdivided into large memory areas for storing large packets of data and small memory areas for storing small packets of data. A packet size determiner determines whether the packet of data to be transferred is a large packet of data or a small packet of data and provides a signal to the DMA controller. In response to this signal, the DMA controller selects a large memory area of the host memory for storing the data when the received data is determined to be a large packet of data and selects a small memory area of the host memory for storing the data when the received data is determined to be a small packet of data.

Abstract: A DMA data transfer system is provided with an interrupt request controller that has pass through logic, data limit logic, stale data logic and error detecting logic to monitor for predetermined conditions. A request for an interrupt sent to a central processor is generated by the interrupt request controller when an input interrupt request is applied to the interrupt request controller and one of the following conditions is met: 1) no previous DMA requests had occurred for a predetermined time interval; 2) a preset limit for the amount of data being transferred is reached; 3) no new requests for DMA transfer occur for preset time intervals; or 4) the status indicates an error in the data being transferred, or priority handling of the data is requested. By making sure one of the predetermined conditions is met before generating an interrupt request, the number of interrupt requests to the central processing unit is greatly reduced and the throughput of the system is increased.

Abstract: A computer system that has a bus is provided with a host memory coupled to the bus, this host memory having an event status queue in which events are stored. A peripheral controller is coupled to the bus and writes a termination marker in a first block in the memory and events occurring in the computer system in blocks in the event status queue in a first direction beginning with a block adjacent to the first block. A host processor is also coupled to the bus. The host processor reads the written events in a second direction opposite to the first direction beginning with a last block in which an event was written by the peripheral controller. The host processor terminates the reading of events when the first block in which the termination marker is reached. The use of a termination marker allows both the hardware of the peripheral controller and the software run by the host processor to operate in the event status queue at the same time, with no danger of running over each other.