Abstract: An apparatus for biasing ultra-low voltage logic circuits is disclosed. An integrated circuit device includes multiple transistors and a global body bias circuit. The global body bias circuit includes a first transistor and second transistors connected in series between a power supply and a second power supply or ground. The gate and source of the first transistor are connected to the first power supply. The gate and source of the second transistor are connected to the second power supply. The drains and bodies of the first and second transistors are connected together to form an output connected to the bodies of the other transistors within the integrated circuit device.

Abstract: A system and method for achieving self-regulated voltage division among multiple serially stacked voltage planes. The system of the present invention is incorporated within a source voltage plane having a source supply node for supplying current and a source ground node for sinking current supplied therefrom. An intermediate voltage supply node is coupled between the source supply voltage node and the source ground node for dividing the source voltage plane into a plurality of intermediate voltage planes. The self-regulated voltage divider of the present invention includes a first capacitor and a second capacitor that are each controllably coupled between either the source supply voltage node and the intermediate voltage supply node, or between the intermediate voltage supply node and the source ground node, such that a voltage level balance is achieved among the intermediate voltage planes.

Abstract: An apparatus for biasing ultra-low voltage logic circuits is disclosed. An integrated circuit device includes multiple transistors and a global body bias circuit. The global body bias circuit includes a first transistor and second transistors connected in series between a power supply and a second power supply or ground. The gate and source of the first transistor are connected to the first power supply. The gate and source of the second transistor are connected to the second power supply. The drains and bodies of the first and second transistors are connected together to form an output connected to the bodies of the other transistors within the integrated circuit device.