Abstract: Techniques and related circuits are disclosed and can be used to characterize glitch performance of a digital-to-analog (DAC) converter circuit in a rapid and repeatable manner, such as for use in providing an alternating current (AC) glitch value specification. A relationship can exist between a glitch-induced DAC output offset value and a DAC circuit input event rate. A relationship between the event rate (e.g., update rate) and the DAC output offset can be used to predict an offset value based at least in part on update rate or to estimate a corresponding glitch impulse area. In particular, a value representing glitch impulse area can be obtained by use of a hardware integration circuit without requiring use of a digitized time-series of glitch event waveforms.

Abstract: Techniques and related circuits are disclosed and can be used to characterize glitch performance of a digital-to-analog (DAC) converter circuit in a rapid and repeatable manner, such as for use in providing an alternating current (AC) glitch value specification. A relationship can exist between a glitch-induced DAC output offset value and a DAC circuit input event rate. A relationship between the event rate (e.g., update rate) and the DAC output offset can be used to predict an offset value based at least in part on update rate or to estimate a corresponding glitch impulse area. In particular, a value representing glitch impulse area can be obtained by use of a hardware integration circuit without requiring use of a digitized time-series of glitch event waveforms.