Patents by Inventor Peter F. Blomley

Peter F. Blomley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5055419
    Abstract: A fully self-aligned polycrystalline silicon emitter bipolar transistor. Self-alignment of the p.sup.+ base contact (12) is achieved by using oxidized sidewalls (8) (sidewall spacers) of the emitter mesa (7) as part of the p.sup.+ base contact implantation mask. Collector contact (13) alignment can be achieved using oxidized sidewalls (17) of polycrystalline silicon alignment mesas (14) defined in the same polysilicon as the emitter mesa (7) but deposited on oxide (2) rather than the implanted base region (5).
    Type: Grant
    Filed: May 17, 1988
    Date of Patent: October 8, 1991
    Assignee: STC, plc
    Inventors: Peter D. Scovell, Peter F. Blomley, Roger L. Baker, Gary J. Tomkins
  • Patent number: 4965216
    Abstract: A process for fabricating a CMOS compatible bipolar transistor is described. The transistor, which is of the polysilicon emitter type, is fabricated by forming a p-type layer in a well, providing a polysilicon emitter in contact with the layer, using the emitter as a mask to implant p.sup.+ -type base contact regions, and applying contacts to the device.
    Type: Grant
    Filed: January 26, 1990
    Date of Patent: October 23, 1990
    Assignee: STC PLC
    Inventors: Peter D. Scovell, Peter F. Blomley, Roger L. Baker
  • Patent number: 4916517
    Abstract: A fully self-aligned polycrystalline silicon emitter bipolar transistor. Self-alignment of the p.sup.+ base contact (12) is achieved by using oxidised sidewalls (8) (sidewall spacers) of the emitter mesa (7) as part of the p.sup.+ base contact implantation mask. Collector contact (13) alignment can be achieved using oxidised sidewalls (17) of polycrystalline silicon alignment mesas (14) defined in the same polysilicon as the emitter mesa (7) but deposited on oxide (2) rather than the implanted base region (5).
    Type: Grant
    Filed: December 5, 1988
    Date of Patent: April 10, 1990
    Assignee: STC, PLC
    Inventors: Peter D. Scovell, Peter F. Blomley, Roger L. Baker, Gary J. Tomkins
  • Patent number: 4914048
    Abstract: A bipolar transistor structure (1) which can be used in an integrated circuit where bipolar (1) and CMOS transistors (2,3) are formed simultaneously on one substrate. In integrated circuit form the material, for example polycrystalline silicon, used for the gates (11,21) of the CMOS transistors is also used for the emitters (29) of the bipolar transistors, the collectors of the bipolar devices are comprised by doped wells (5) in the substrate (4) and the base contacts of the bipolar devices are comprised by regions (27,27a) equivalent to source and drain regions (17,18) of the n-well MOS transistors and bridged by base implants (28). The conventional CMOS processing is modified by the addition of two masking steps and one implant (base implant).
    Type: Grant
    Filed: December 16, 1987
    Date of Patent: April 3, 1990
    Assignee: STC plc
    Inventors: Peter D. Scovell, Peter F. Blomley, Roger L. Baker
  • Patent number: 4893117
    Abstract: A drive circuit for a liquid crystal display uses a sampling technique to derive drive signals from a pair of input waveforms. The waveforms comprise positive going and negative going trapezoidal pulses. By sampling the waveforms at appropriate points, single cycle AC signals and zero voltage signals can be provided. The technique subjects the drive circuit to a voltage stress that is lower than that provided by conventional techniques.
    Type: Grant
    Filed: July 17, 1987
    Date of Patent: January 9, 1990
    Assignee: STC PLC
    Inventors: Peter F. Blomley, Peter J. Ayliffe, Ewen R. M. Huffman, Gregory W. M. Yuen
  • Patent number: 4849364
    Abstract: A method of manufacturing a bipolar transistor (1) with semi-self-aligned p.sup.+ base contacts (27,27a). A p-type base region (28) is formed in a surface region of an n-type region 5 comprising a collector. An element (29) of, for example, n.sup.+ doped polycrystalline silicon, and comprising an emitter, is formed on the surface in contact with the base region (28). The base contacts (27,27a) are formed by implantation and using the element (29) as a mask. An n.sup.+ collector contact (25) is made to the n-tpe region (5).
    Type: Grant
    Filed: December 16, 1987
    Date of Patent: July 18, 1989
    Assignee: STC PLC
    Inventors: Peter D. Scovell, Peter F. Blomley, Roger L. Baker
  • Patent number: 4845532
    Abstract: A bipolar transistor structure (1) which can be used in an integrated circuit where bipolar (1) and CMOS transistors (2,3) are formed simultaneously on one substrate. In integrated circuit form the material, for example polycrystalline silicon, used for the gates (11,21) of the CMOS transistors is also used for the emitters (29) of the bipolar transistors, the collectors of the bipolar devices are comprised by doped wells (5) in the substrate (4) and the base contacts of the bipolar devices are comprised by regions (27,27a) equivalent to source and drain regions (17,18) of the n-well MOS transistors and bridged by base implants (28). The conventional CMOS processing is modified by the addition of two masking steps and one implant (base implant).
    Type: Grant
    Filed: December 13, 1988
    Date of Patent: July 4, 1989
    Assignee: STC PLC
    Inventors: Peter D. Scovell, Peter F. Blomley, Roger L. Baker
  • Patent number: 4748664
    Abstract: To provide an adequate dc supply to the electronics of a telephone, when on hook or off hook, there is a transistor (T2) with its emitter-collector path in one line wire, and a storage capacitor (Cpsu) across the input to the telephones's circuits. This capacitor is charged up and maintains dc supply when the line voltage (at A) falls below a preset level. The base of this transistor is connected via another transistor (T1) to the other line wire. The speech output (V.sub.IN) is connected via an operational amplifier (A) to the base of the second transistor (T2). Hence the dc supply and the speech output are in parallel.
    Type: Grant
    Filed: November 14, 1986
    Date of Patent: May 31, 1988
    Assignee: STC Plc
    Inventor: Peter F. Blomley
  • Patent number: 4745080
    Abstract: A fully self-aligned polycrystalline silicon emitter bipolar transistor. Self-alignment of the p.sup.+ base contact (12) is achieved by using oxidized sidewalls (8) (sidewall spacers) of the emitter mesa (7) as part of the p.sup.+ base contact implantation mask. Collector contact (13) alignment can be achieved using oxidized sidewalls (17) of polycrystalline silicon alignment mesas (14) defined in the same polysilicon as the emitter mesa (7) but deposited on oxide (2) rather than the implanted base region (5).
    Type: Grant
    Filed: February 20, 1986
    Date of Patent: May 17, 1988
    Assignee: STC, plc
    Inventors: Peter D. Scovell, Peter F. Blomley, Roger L. Baker, Gary J. Tomkins
  • Patent number: 4608462
    Abstract: An integrated circuit for a telephone instrument provides the basic (POT) service requirement. The transmit and receive channels of the circuit may be fed via controlled attenuators incorporated in a first ancillary circuit to provide hands-free operation. The circuit also includes a current-limited power supply whereby connection to a second ancillary circuit, including an audio amplifier, may be effected to provide loudspeaker operation.
    Type: Grant
    Filed: October 19, 1984
    Date of Patent: August 26, 1986
    Assignee: International Standard Electric Corporation
    Inventors: Peter F. Blomley, Kenneth A. Arton, Edward J. Whittaker, Andrew P. Lefevre
  • Patent number: 4555596
    Abstract: In a loudspeaking telephone it is necessary to ensure that pick-up by the microphone of sound from the loudspeaker does not set up a howling condition. To do this it is usual to disable either the transmitting or the receiving speech channel.To do this, the signal from each channel is applied to an analogue-digital signal envelope converter (30,31), which generates a multi-bit word representative of the current speech amplitude in its channel. Those words are applied to a comparator (32) whose output is indicative of which channel passes speech. Such a converter follows the envelope of the speech signal in its channel to produce the multi-bit word representing the current speech amplitude in its channel. The comparator's output goes via control logic (33) to two attenuators (34, 35), one in each channel. Thus only the channel which is actually passing speech, or the one with the higher speech amplitude, is enabled.
    Type: Grant
    Filed: June 7, 1983
    Date of Patent: November 26, 1985
    Assignee: International Standard Electric Corporation
    Inventor: Peter F. Blomley
  • Patent number: 4506113
    Abstract: A soft clipping circuit for a telephone subset limits the output signal amplitude to the line thus preventing output stage saturation with consequent reduction in impedance. The circuit includes a variable gain input stage (I/P), a main speech signal amplifier (AMP1) and a rectifying amplifier feed back stage (AMP2) that generates a control current whenever the output speech signal exceeds a predetermined threshold. This current is fed to the input stage so as to reduce its gain. Typically the input stage comprises a long tailed transistor pair amplifier, the control current being fed to the tail of the pair.
    Type: Grant
    Filed: May 5, 1983
    Date of Patent: March 19, 1985
    Assignee: International Standard Electric Corporation
    Inventor: Peter F. Blomley
  • Patent number: 4502018
    Abstract: A gain regulation circuit e.g. for a telephone subscriber's instrument, includes a plurality (2n+1) of long tailed transistor pairs one of which has a significantly higher gain than the remainder (2n). The circuit may be adjusted to a composite gain value between limits defined by the high and low gain pairs by providing a suitably weighted combination of these pairs. Typically, this weighting is achieved by control currents fed into the tail circuits of the pairs.
    Type: Grant
    Filed: May 5, 1983
    Date of Patent: February 26, 1985
    Assignee: International Standard Electric Corporation
    Inventor: Peter F. Blomley
  • Patent number: 4347407
    Abstract: A telephone instrument circuit including electronic components for functions such as amplifying incoming and outgoing speech signals. When the electronic transducers of each electronic instruments have to operate in parallel with a carbon microphone in another instrument, problems are likely to arise. To deal with the problem, a voltage regulator is used which includes two essentially series coupled comparator-amplifiers, the first of which is driven by the circuit's supply voltage. The second amplifier has its own reference voltage and its output varies the reference voltage V.sub.R for the first amplifier, whose output is connected to the line whose voltage is being regulated. Above a preset line current, the I-V characteristic of the circuit is almost flat while below the preset threshold it is fairly steep to enable satisfactory parallel operation.
    Type: Grant
    Filed: August 27, 1980
    Date of Patent: August 31, 1982
    Assignee: International Standard Electric Corporation
    Inventor: Peter F. Blomley
  • Patent number: 4286123
    Abstract: A four-transistor bridge amplifier is adapted for use as a bidirectional speech amplifier between a telephone line and an electronic telephone subscriber's instrument. The amplifier is powered from the line and includes two-transistor sections, one or other of which functions dependent on line polarity. The output of the amplifier to the subscriber instrument is taken across a resistor connected between the transistors such that the output always has the same relative polarity whatever the line polarity.
    Type: Grant
    Filed: March 15, 1979
    Date of Patent: August 25, 1981
    Assignee: International Standard Electric Corporation
    Inventor: Peter F. Blomley
  • Patent number: 4127825
    Abstract: A quadrature phase detector having a tuned circuit connected between inputs thereof with a voltage variable reactance connected therein and further connected to the output of the phase detector for tuning the tuned circuit in accordance with the output of the phase detector, and a voltage variable capacitor in the tuned circuit connected to receive a signal from a comparator which compares the output of the phase detector to a reference signal so that a signal having a predetermined frequency can be applied to the input of the phase detector and the tuned circuit of the phase detector is tuned to a predetermined reference frequency. The tuned circuit input of the phase detector continually tracks the input signal, which may be a FM color subcarrier signal. Additionally, there is compensation for the inherent nonlinearity in the tuned circuit.
    Type: Grant
    Filed: April 6, 1977
    Date of Patent: November 28, 1978
    Assignee: Motorola, Inc.
    Inventor: Peter F. Blomley