Patents by Inventor Peter F. Curran

Peter F. Curran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Encoding and decoding architecture and method for pipelining encoded data or pipelining with a look-ahead strategy
    Patent number: 7933354
    Abstract: An encoding and/or decoding communication system comprises a framer interface, an encoder, a multiplexer, an output driver, and a clock multiplier unit (CMU). The encoder includes an input latch circuitry stage; an output latch circuitry stage; an intermediate latch circuitry stage interposed between the input latch circuitry stage and the output latch circuitry stage, the intermediate latch circuitry stage coupled to the input latch circuitry stage and the output latch circuitry stage; a plurality of encoding logic circuitry stages interposed between the input latch circuitry stage and the output latch circuitry stage, a last one of the plurality of encoding logic circuitry stages placed adjacent to the output latch circuitry stage and coupled to the output latch circuitry stage; and a feedback between the output latch circuitry stage and the last one of the plurality of encoding logic circuitry stages.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: April 26, 2011
    Assignee: Semtech Corporation
    Inventors: Samuel A. Steidl, Peter F. Curran
  • Encoding and decoding architecture and method for pipelining encoded data or pipelining with a look-ahead strategy
    Publication number: 20080118246
    Abstract: An encoding and/or decoding communication system comprises a framer interface, an encoder, a multiplexer, an output driver, and a clock multiplier unit (CMU). The encoder includes an input latch circuitry stage; an output latch circuitry stage; an intermediate latch circuitry stage interposed between the input latch circuitry stage and the output latch circuitry stage, the intermediate latch circuitry stage coupled to the input latch circuitry stage and the output latch circuitry stage; a plurality of encoding logic circuitry stages interposed between the input latch circuitry stage and the output latch circuitry stage, a last one of the plurality of encoding logic circuitry stages placed adjacent to the output latch circuitry stage and coupled to the output latch circuitry stage; and a feedback between the output latch circuitry stage and the last one of the plurality of encoding logic circuitry stages.
    Type: Application
    Filed: December 18, 2006
    Publication date: May 22, 2008
    Applicant: SIERRA MONOLITHICS, INC.
    Inventors: Samuel A. Steidl, Peter F. Curran