Abstract: Printed circuit board having a termination of a T-shaped signal line having at least two line ends, one line end being terminated using a terminating resistor against a supply voltage, and the other line end being terminated against the reference potential of the supply voltage.

Abstract: Printed circuit board having a termination of a T-shaped signal line having at least two line ends, one line end being terminated using a terminating resistor against a supply voltage, and the other line end being terminated against the reference potential of the supply voltage.

Abstract: The invention relates to a method for displaying a television picture or monitor picture on a display screen. In order to achieve a largely line-free display while degrading the vertical contrast of the picture as little as possible, an approach is proposed in which a vertical contrast value is determined from a video input signal (Y), the vertical contrast value is compared with a limiting value (a, b), and a vertical widening of a light spot region of the lines covered by the scanning beam is set as a function of this comparison, preferably by a vertical sweep of the scanning beam. If the vertical contrast value is below the limiting value (a, b), a smaller vertical widening of the light spot region is set than if the vertical contrast value is above the limiting value (a, b).

Abstract: A digital phase-locked loop has a periodically overflowing digital oscillator (DCO), implemented as a modulo adder, and a processor device. The processor device adjusts the period T of the digital oscillator to a nominal period, determined from periodically occurring synchronizing pulses, by comparing the actual phase of the digital oscillator with a set phase at the control clock rate of the periodic synchronizing pulses. After the digital oscillator has been locked to the nominal period, the processor device compares the phases by using a double-frequency signal sequence of one-half line period derived from the digital oscillator output signal. The DCO output signal is fed to a correction device where an address-phase signal, locked to the DCO output signal, is generated so that when a non-periodic synchronizing pulse occurs, the address-phase signal is shifted by one period of the signal sequence of one-half line period with respect to the digital oscillator output signal.