Patents by Inventor Peter Fleischmann

Peter Fleischmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7714641
    Abstract: A voltage regulator arrangement having a first voltage regulator, whose input connection is connected to the supply potential connection and whose output connection is connected to a first supply potential connection of a circuit arrangement, with the first voltage regulator supplying the circuit arrangement with a supply voltage in a rest state. A second voltage regulator is also provided, whose input connection is connected to the supply potential connection, and whose output connection is connected to a second supply potential connection of the circuit arrangement, with the second voltage regulator supplying the circuit arrangement with a supply voltage during its normal operation.
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: May 11, 2010
    Assignee: Infineon Technologies AG
    Inventors: Peter Fleischmann, Gerhard Nebel, Andreas Schlaffer, Uwe Weder
  • Patent number: 7398493
    Abstract: A technique for checking a layout design of an integrated circuit is disclosed. The technique has application to converting the design of a circuit from schematic to layout form. Instances where multiple pwell isolation tanks are coupled to the same node and where one or more pwell isolation tanks are shorted to a substrate are detected. Node breakers are inserted in the layout between pwell isolation tanks coupled to the same node and between the substrate and isolated pwell tanks coupled to the substrate. The node breakers are inserted in the circuit schematic as well to satisfy a layout versus schematic comparison. Inserting the node breakers highlights circuit component groupings as well as which tanks contain certain elements, if any. This allows designers to make a conscious decision as to the location and groupings of elements in a layout design.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: July 8, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Haim Horovitz, Mark Allenspach, Peter Fleischmann
  • Publication number: 20070214441
    Abstract: A technique for checking a layout design of an integrated circuit is disclosed. The technique has application to converting the design of a circuit from schematic to layout form. Instances where multiple pwell isolation tanks are coupled to the same node and where one or more pwell isolation tanks are shorted to a substrate are detected. Node breakers are inserted in the layout between pwell isolation tanks coupled to the same node and between the substrate and isolated pwell tanks coupled to the substrate. The node breakers are inserted in the circuit schematic as well to satisfy a layout versus schematic comparison. Inserting the node breakers highlights circuit component groupings as well as which tanks contain certain elements, if any. This allows designers to make a conscious decision as to the location and groupings of elements in a layout design.
    Type: Application
    Filed: March 13, 2006
    Publication date: September 13, 2007
    Inventors: Haim Horovitz, Mark Allenspach, Peter Fleischmann
  • Publication number: 20050057299
    Abstract: A voltage regulator arrangement having a first voltage regulator, whose input connection is connected to the supply potential connection and whose output connection is connected to a first supply potential connection of a circuit arrangement, with the first voltage regulator supplying the circuit arrangement with a supply voltage in a rest state. A second voltage regulator is also provided, whose input connection is connected to the supply potential connection, and whose output connection is connected to a second supply potential connection of the circuit arrangement, with the second voltage regulator supplying the circuit arrangement with a supply voltage during its normal operation.
    Type: Application
    Filed: September 20, 2004
    Publication date: March 17, 2005
    Applicant: Infineon Technologies AG
    Inventors: Peter Fleischmann, Gerhard Nebel, Andreas Schlaffer, Uwe Weder