Abstract: A semiconductor component and a method for manufacturing such a semiconductor component which has a resistance behavior which depends heavily on the temperature. This resistance behavior is obtained by a special multi-layer structure of the semiconductor component, one layer being designed in such a way that, for example, multiple p-doped regions are present in an n-doped region, said regions being short-circuited on one side via a metal-plated layer. For example, the semiconductor component may be used for reducing current peaks, by being integrated into a conductor. In the cold state, the semiconductor component has a high resistance which becomes significantly lower when the semiconductor component is heated as a result of the flowing current.

Abstract: A semiconductor component and a method for manufacturing such a semiconductor component which has a resistance behavior which depends heavily on the temperature. This resistance behavior is obtained by a special multi-layer structure of the semiconductor component, one layer being designed in such a way that, for example, multiple p-doped regions are present in an n-doped region, said regions being short-circuited on one side via a metal-plated layer. For example, the semiconductor component may be used for reducing current peaks, by being integrated into a conductor. In the cold state, the semiconductor component has a high resistance which becomes significantly lower when the semiconductor component is heated as a result of the flowing current.

Abstract: A semiconductor power component and a method for producing a semiconductor power component, in particular a vertical NPT-IGBT for ignition applications with a breakdown voltage of less than approx. 1000 V. The semiconductor power component includes a wafer substrate of a first conductive type including a rear-side emitter region of a second conductive type and a front-side drift region of the first conductive type; a rear-side anode contact which is connected to the emitter region and extends partially to the front-side surface; a front-side MOS control structure; and a front-side cathode contact which is connected to a front-side source region and a body region of the front-side MOS control structure. The thickness of the drift region is much larger than the width of the space charge region at a defined breakdown voltage; and the thickness of the rear-side emitter region is greater than 5 ?m.

Abstract: A semiconductor power component and a method for producing a semiconductor power component, in particular a vertical NPT-IGBT for ignition applications with a breakdown voltage of less than approx. 1000 V. The semiconductor power component includes a wafer substrate of a first conductive type including a rear-side emitter region of a second conductive type and a front-side drift region of the first conductive type; a rear-side anode contact which is connected to the emitter region and extends partially to the front-side surface; a front-side MOS control structure; and a front-side cathode contact which is connected to a front-side source region and a body region of the front-side MOS control structure. The thickness of the drift region is much larger than the width of the space charge region at a defined breakdown voltage; and the thickness of the rear-side emitter region is greater than 5 &mgr;m.

Abstract: A vertical semiconductor component has an integrated switching device, which delivers an electric value correlating with the rear potential. The semiconductor component includes a doping region with a hole, which is free of the doping atoms of the doping region. The hole, when properly sized and contacted, can supply an electric current correlating with the rear potential.

Abstract: The composite hybrid semiconductor structure contains a support plate substrate (11) with a number of at least two support connector spots (13) and a semiconductor chip or semiconductor wafer substrate (10) with a number of at least two chip connector spots (16). The structures is distinguished by a respectively thermally and electrically conducting adhesive layer (13') on the surface of the support plate substrate (11) within the areas of the support connector spots (13), where the said substrates (10, 11) with the said connector spots (13, 16) placed opposite each other and in electrically conducting and mechanically firm connection have been brought into connection with each other by the said electrically conductive adhesive layers (13').

Abstract: The invention relates to a monolithically integrated semiconductor arrangement, where from the first main surface a first zone (p) and a second zone (n.sup.+) are diffused into a substrate (2), which is weakly doped (substrate region n.sup.-) under a first main surface (3) and is more strongly doped (substrate region n.sup.+) under a second main surface (4). An insulating passivation layer is attached to the first main surface (3), on top of which a metallic cover electrode (D) is located, which covers adjacent substrate regions (n.sup.-) and the edge areas of the first zone (p) and the second zone (n.sup.+). In accordance with the invention, at least one additional zone (.nu.) of the same type of conductivity as the associated zone (n.sup.+), but with weaker doping, is diffused in for increasing the break-through voltage, and is connected to the zone (n.sup.+), does not contact the other zone (p) and prevents the zone (n.sup.+) from directly bordering the substrate (n.sup.

Abstract: A monolithic integrated semiconductor is proposed, in which on the main surface of a monolithically integrated n-p-n transistor or p-n-p transistor, a cover electrode (D1) is mounted for internal voltage limitation, covering only a single junction region between a highly doped zone (5) and the weakly doped substrate (1). An adjacent highly doped zone (4) is not covered by the cover electrode (D1). By connecting the metal cover electrode (D1) to the pickup (12) for a voltage divider (R1, R2), a breakdown voltage can be adjusted that is higher than the sum of the depletion breakdown voltage and the enhancement breakdown voltage.

Abstract: A monolithic integrated semiconductor device is described, wherein for the adjustment of the breakdown voltage a cover electrode (7) is disposed in the area of the pn-junctions and a corresponding potential is applied through a voltage divider (1) for adjusting the breakdown voltage. For maintaining a temperature independent breakdown voltage it is provided that the voltage divider (1) consists of resistors (R1, R2) in the form of diffused zones which have different doping levels. The resulting different temperature coefficients of the resistors (R1,R2) of the voltage divider cause a temperature dependent potential change of the cover electrode potential, whereby a temperature stabilization of the breakdown voltage is obtained.

Abstract: A transistor arrangement, particularly for the fast switching of inductive loads, includes a driving first transistor and a power output second transistor (T1, T2) interconnected as a Darlington pair having a base terminal, an emitter terminal and a collector terminal. A third transistor (T3) has its collector connected to the base of the first transistor (T1) and its emitter connected to the emitter terminal (E). A fourth transistor (T4) of a conductivity type opposite to that of the first, second and third transistors has its base connected to the collector terminal, its emitter connected to the base terminal, and its collector connected to the base of the third transistor (T3). This structure is particularly suited for a monolithic integration.

Abstract: A semiconductor arrangement is suggested which is provided with a capacity transistor and a drive transistor in form of a Dralington-circuit. Thereby, the two transistors are monolithically integrated with a planar technique in a common substrate (8), which forms the two collector zones of the two transistors (T1,T2). A passivation layer (14) covers the main face of substrate (8) covering this main surface with the exception of contact windows. A cover electrode (13) is disposed above the passivation layer in the area between the collector zone and the base zone (4) of the capacity transistor (T2), whereby this passivation layer is connected with a resistor strip (2) at a distance from the base zone (4) for adjusting its potential. An additional guard strip (3) is diffused into the main surface between the resistor strip (2) and the base zone (4).

Abstract: A Darlington transistor circuit having a power transistor and a driver transistor is proposed. The two transistors are monolithically integrated in a common substrate (10) by a planar process, the substrate forming the collector zones of the two transistors. On the main surface of the substrate (10) there is a passivation layer (13) covering this main surface with the exception of contact windows. The base-collector junctions of the two transistors are protected by a metal electrode (15), which is located above the passivation layer (13) and extends up to a stop ring (14), which is disposed beneath the passivation layer (13) in the substrate (10). The potential at the cover electrode (15) is adjustable with the aid of a voltage divider (16). (FIG. 3).

Abstract: A planar semiconductor structure is proposed which has a monocrystalline semiconductor chip (10) of a specific conductivity type, a first zone (11) of the opposite conductivity type introduced into the semiconductor chip (10) by diffusion from a main surface and together with the material making up the semiconductor chip (10) forming a p-n junction (12), and a passivation layer (13) covering this same main surface of the semiconductor chip (10) with the exception of contact windows. A second, annular zone (14) acting as a stop ring and having the same conductivity type as the basic material making up the semiconductor chip (10) but a higher concentration of impurities is introduced into the semiconductor chip (10) from the same main surface such that it surrounds the first zone (11).

Abstract: In a three-stage Darlington transistor circuit, the base of the middle transistor is connected to the series combination of a resistance and a Zener diode, with the Zener diode anode being connected to the resistance. A voltage divider is provided between the collector and emitter of the power transistor. For reducing the loading and deviation from nominal value of the voltage divider with change of temperature, an auxiliary transistor (T.sub.4) is provided having its base connected to one tap of the voltage divider and its emitter to the cathode of the Zener diode. The collector of the auxiliary transistor is provided in the integrated circuit substrate in common with the collectors of the transistors of the Darlington circuit. The other tap of the voltage divider is provided for emitter-collector clamping voltage purposes.

Abstract: A semiconductor electrode is prepared by (a) contacting a semiconductor w a first contacting metal (capable of forming an alloy with the semiconductor), (b) contacting the first contacting metal with a ductile layer of a second contacting metal, (c) heating the resulting combination so as to form, simultaneously, a liquid phase between the semiconductor and the first contacting metal and between the first contacting metal and the ductile second contacting metal, however leaving intact a major portion of the ductile second contacting metal layer, and (d) cooling the thus obtained product whereby a solder contact which is resistant to load fluctuations can be readily made on the ductile layer with known semiconductor hard solder.