Abstract: Techniques for task processing based on a parallel processing architecture using distributed register files are disclosed. A two-dimensional array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring compute elements. The array of compute elements is controlled on a cycle-by-cycle basis. The controlling is enabled by a stream of wide control words generated by the compiler. Virtual registers are mapped to a plurality of physical register files distributed among one or more of the compute elements. Virtual registers are represented by the compiler. The mapping is performed by the compiler. A broadcast write operation is enabled to two or more of the physical register files. Operations contained in the control words are executed. Operations are enabled by at least one of the distributed physical register files. Implementation in separate compute elements enables parallel operation processing.

Abstract: Techniques for task processing based on a parallel processing architecture with distributed register files are disclosed. A two-dimensional array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring compute elements. The array of compute elements is controlled on a cycle-by-cycle basis. The controlling is enabled by a stream of wide, variable length, control words generated by the compiler. Virtual registers are mapped to a plurality of physical register files distributed among one or more of the compute elements. Virtual registers are represented by the compiler. The mapping is performed by the compiler. A broadcast write operation is enabled to two or more of the physical register files. Operations contained in the control words are executed. Operations are enabled by at least one of the distributed physical register files. Implementation in separate compute elements enables parallel operation processing.

Abstract: Implementations described and claimed herein include a cushioning structure and method for manufacturing a cellular cushioning system, which allows for maximum comfort through the compression and shock cycle. Specifically, a cushioning structure comprises void cells formed in an array, which comprise multiple outwardly curved surfaces, with varying radius measurements. Stiffness in the void cells can vary by varying the radii. The outwardly curved surfaces prevent buckling and provide support for high impact by absorbing energy.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to determine memory access integrity based on feedback from memory. An example apparatus includes an access reconstruction controller including an output, a first input configured to be coupled to memory, and a second input configured to be coupled to a memory signal generator; a comparator including a first input coupled to the output of the access reconstruction controller, a second input configured to be coupled to an arbiter, and an output configured to be coupled to the arbiter; and a data integrity monitor including an input coupled to the second input of the comparator and configured to be coupled to the arbiter and an output coupled to the output of the comparator and configured to be coupled to the arbiter.

Abstract: Techniques for program execution in a parallel processing architecture using speculative encoding are disclosed. A two-dimensional array of compute elements is accessed, where each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the array of compute elements is provided on a cycle-by-cycle basis. The control is enabled by a stream of wide, variable length, control words generated by the compiler. Two or more operations are coalesced into a control word, where the control word includes a branch decision and operations associated with the branch decision. The coalesced control word includes speculatively encoded operations for at least two possible branch paths. The at least two possible branch paths generate independent side effects. Operations associated with the branch decision that are not indicated by the branch decision are suppressed.

Abstract: A shoe sole comprises a first array of interconnected void cells that is oriented adjacent to a second opposing array of interconnected void cells, wherein the second opposing array of interconnected void cells is geometrically different from the first array of void cells and includes at least one void cell with an asymmetrical perimeter.

Abstract: The present disclosure provides a method for treating clinical or pre-clinical skin damage in a skin field of a subject, wherein the skin field has been allocated a skin cancerization field index (SCR) score of at least 1 as determined by a process comprising the steps of: (i) assessing the number of keratoses in the skin field; (ii) assessing the thickness of the thickest keratosis in the skin field; and (iii) assessing the proportion of the field affected by clinical or subclinical skin damage. Based on the assessments made in (i), (ii) and (iii) the subject is optionally treated by at least one of (a) freezing one or more lesions, (b) shaving, curetting or surgically removing one or more lesions, (c) applying a topical treatment for actinic keratosis, basal cell carcinoma or squamous cell carcinoma, and (d) radiation therapy.

Abstract: Techniques for task processing in a highly parallel processing architecture using dual branch execution are disclosed. A two-dimensional array of compute elements is accessed. Each compute element within the array is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the array of compute elements is provided on a cycle-by-cycle basis. The control is enabled by a stream of wide, variable length, control words generated by the compiler. The control includes a branch. Two sides of the branch in the array are executed while waiting for a branch decision to be acted upon by control logic. The branch decision is based on computation results in the array. Data produced by a taken branch path is promoted. Results from a side of the branch not indicated by the branch decision are ignored or invalidated.

Abstract: Techniques for task processing using a highly parallel processing architecture with a shallow pipeline are disclosed. A two-dimensional array of compute elements is accessed. Each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the array of compute elements is provided on a cycle-by-cycle basis. The control is enabled by a stream of wide, variable length, microcode control words generated by the compiler. Relevant portions of the control word are stored within a cache associated with the array of compute elements. The control words are decompressed. The decompressing occurs cycle-by-cycle out of the cache over multiple cycles. A compiled task is executed on the array of compute elements, based on the decompressing. Simultaneous execution of two or more potential compiled task outcomes is provided.

Abstract: Techniques for task processing using a parallel processing architecture with background loads are disclosed. A two-dimensional array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring compute elements. Operation of the array is paused. The pausing occurs while a memory system continues operation. A bus coupling the array is repurposed. The repurposing couples one or more compute elements in the array to the memory system. A memory system operation is enabled during the pausing. Data is transferred from the memory system to the array of compute elements using the bus that was repurposed. The data from the memory system is transferred to scratchpad memory in the one or more compute elements within the two-dimensional array. The scratchpad memory provides operand storage. The data is tagged. The tagging guides the transferring to a particular compute element.

Abstract: Techniques for task processing using a highly parallel processing architecture with a compiler are disclosed. A two-dimensional array of compute elements is accessed. Each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. A set of directions is provided to the hardware, through a control word generated by the compiler, for compute element operation and memory access precedence. The set of directions enables the hardware to properly sequence compute element results. The set of directions controls data movement for the array of compute elements. A compiled task is executed on the array of compute elements, based on the set of directions. The compute element results are generated in parallel in the array, and the compute element results are ordered independently from control word arrival at each compute element.

Abstract: The present disclosure provides a method for treating clinical or pre-clinical skin damage in a skin field of a subject, wherein the skin field has been allocated a skin cancerization field index (SCFI) score of at least 1 as determined by a process comprising the steps of: (i) assessing the number of keratoses in the skin field; (ii) assessing the thickness of the thickest keratosis in the skin field; and (iii) assessing the proportion of the field affected by clinical or subclinical skin damage. Based on the assessments made in (i), (ii) and (iii) the subject is optionally treated by at least one of (a) freezing one or more lesions, (b) shaving, curetting or surgically removing one or more lesions, (c) applying a topical treatment for actinic keratosis, basal cell carcinoma or squamous cell carcinoma, and (d) radiation therapy.

Abstract: Implementation described and claimed herein include a cushioning structure and method for manufacturing a cellular cushioning system, which allows for maximum comfort through the compression and shock cycle. Specifically, a cushioning structure comprises void cells formed in an array, which comprise multiple outwardly curved surfaces, with varying radius measurements. Stiffness in the void cells can vary by varying the Radii. Outwardly curved surfaces prevent buckling and provide support for high impact by absorbing energy.

Abstract: The present disclosure provides a method for treating clinical or pre-clinical skin damage in a skin field of a subject, wherein the skin field has been allocated a skin cancerization field index (SCFI) score of at least 1 as determined by a process comprising the steps of: (i) assessing the number of keratoses in the skin field; (ii) assessing the thickness of the thickest keratosis in the skin field; and (iii) assessing the proportion of the field affected by clinical or subclinical skin damage. Based on the assessments made in (i), (ii) and (iii) the subject is optionally treated by at least one of (a) freezing one or more lesions, (b) shaving, curetting or surgically removing one or more lesions, (c) applying a topical treatment for actinic keratosis, basal cell carcinoma or squamous cell carcinoma, and (d) radiation therapy.

Abstract: A system is provided that enables a process centralized from a pharmacy or online portal which allows an individual to access authorized international laboratory tests and results with clinical input to track, monitor and improve their personal health. The system commands a network of global physician portals to approve; review patients requests and support to derive better clinical outcomes. The accounts are linked to anonymized system using patient identifiers and real-time test code assignment to ensure a seamless and confidential exchange of data.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for safety mechanisms to actively detect address faults. An example system includes a first parity generator, a second parity generator, and a parity checker. The first parity generator is to generate a first parity based on a first address information. The first address information corresponds to a desired location to store data in a memory storage array. The second parity generator is to generate a second parity based on a second address information. The second address information corresponding to an actual location where the data is stored in the memory storage array. The parity checker is to compare the first parity and the second parity to detect a fault.

Abstract: A shoe sole comprises a first array of interconnected void cells that is oriented adjacent to a second opposing array of interconnected void cells, wherein the second opposing array of interconnected void cells is geometrically different from the first array of void cells and includes at least one void cell with an asymmetrical perimeter.

Abstract: A shoe sole comprises a first array of interconnected void cells that is oriented adjacent to a second opposing array of interconnected void cells, wherein the second opposing array of interconnected void cells is geometrically different from the first array of void cells and includes at least one void cell with an asymmetrical perimeter.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for safety mechanisms to actively detect address faults. An example system includes a first parity generator, a second parity generator, and a parity checker. The first parity generator is to generate a first parity based on a first address information. The first address information corresponds to a desired location to store data in a memory storage array. The second parity generator is to generate a second parity based on a second address information. The second address information corresponding to an actual location where the data is stored in the memory storage array. The parity checker is to compare the first parity and the second parity to detect a fault.

Abstract: A system includes a central processing unit (CPU) core, and a pulse width modulator (PWM) controller configured to generate a PWM control signal having a PWM cycle. The system also includes an analog-to-digital converter (ADC), an accumulator, a sum register, and an oversampling register set. The oversampling register set is configurable by the CPU core to specify time points during each PWM cycle when the ADC is to convert an analog signal to a digital sample to produce a plurality of digital samples. The time spacing between consecutive digital samples varies among the specified time points. The accumulator accumulates digital samples from the ADC and stores an accumulated sum in the sum register. The CPU core reads the accumulated sum from the sum register, and can use the accumulated sum to calculate a metric (e.g., an average) of the digital samples.