Abstract: A method and apparatus are provided for implementing power saving in a content addressable memory (CAM). A compare array is matched against a key and if a match occurs then logic coupled to the compare array generates a hit signal. A data array includes precharge circuitry and data output latches to capture the data output. A clock gate coupled to the logic provides clock signals to the output latches and precharge circuitry of the data array when a hit occurs. When a hit does not occur, the clock signals are gated off to the output latches and precharge circuitry of the data array.

Abstract: A latching dynamic logic includes a dynamic logic gate, a static logic input interface, and a set-reset output latch. The dynamic logic gate receives a clock signal, a data signal, and a select signal output of the static logic input interface. The dynamic logic gate includes a dynamic node and a pulldown network coupled to the dynamic node. The pulldown network selectively discharges the dynamic node following a clock signal transition dependent on the data signal and the select signal output of the static logic input interface being active. The set-reset output latch is coupled to the dynamic node of the dynamic logic gate for providing an output signal.

Abstract: In a first aspect, a first method is provided for writing an LRU indicator. The first method includes the steps of (1) activating one of a first word line that corresponds to a first memory array and a second word line which corresponds to a second memory array; (2) employing the first word line, when activated, for writing to the first memory array and for writing the LRU indicator; and (3) employing the second word line, when activated, for writing to the second memory array and for writing the LRU indicator. Numerous other aspects are provided.

Abstract: In a first aspect, a first method is provided for testing an integrated circuit (IC). The first method includes the steps of (1) selecting a bit from each of a plurality of memory arrays formed on an IC chip; (2) selecting one of the plurality of memory arrays; and (3) storing the selected bit from the selected memory array. Numerous other aspects are provided.

Abstract: The present invention provides for reading indicia from an SRAM cell. A low value is generated on a write true line. A high value is generated on a continuous bit_line. The true node of the SRAM cell is evaluated through use of a floating voltage coupled to the true node of the SRAM cell. If the floating voltage stays substantially constant, the value read from the SRAM cell is a high. If the floating voltage is drained to ground, the value read from the SRAM cell is a low.