Abstract: A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A memory structure comprises a memory storage element, a control element comprising a tunnel-junction device electrically coupled to the memory storage element and configured to control the state of the memory storage element, and a reference element. The reference element is configured as a reference to protect the control element when selectively controlling the state of the memory storage element.

Abstract: A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A memory structure comprises a memory storage element, a control element comprising a tunnel-junction device electrically coupled to the memory storage element and configured to control the state of the memory storage element, and a reference element. The reference element is configured as a reference to protect the control element when selectively controlling the state of the memory storage element.

Abstract: A memory cell includes a heating component that is connected to a voltage-breakdown component. The heating component is configured to accelerate the break-down of a voltage-breakdown component. Memory structures and methods for making them are also disclosed.

Abstract: Disclosed are improved cross-point array memory devices. In one embodiment, a memory device comprises a cross-point array of memory cells, each memory cell including a storage element and a current concentrating feature that concentrates current applied to the storage element. In another embodiment, a memory device comprises a cross-point array of memory cells, each memory cell including a storage element having a preprogrammed filament fuse configured to be disabled during a write procedure.

Abstract: A memory storage device includes a memory cell configurable to have at least a first conductive state and includes a first and second conductor each electrically coupled to the memory cell. A regulation circuit is configured to regulate a sense voltage on the second conductor to be independent of a current conducted through the first conductor when the memory cell is configured to have the first conductive state.

Abstract: A memory structure that includes a first electrode, a second electrode, a thermal conduction limiting electrode having a thermal conductivity that is less than a thermal conductivity of the first electrode, a memory storage elementdisposed between the thermal conduction limiting electrode and the second electrode, and a control element disposed between the second electrode and the first electrode.

Abstract: A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A memory structure comprises a memory storage element, a control element comprising a tunnel-junction device electrically coupled to the memory storage element and configured to control the state of the memory storage element, and a reference element. The reference element is configured as a reference to protect the control element when selectively controlling the state of the memory storage element.

Abstract: A memory structure that includes a control element electrode, a heater electrode, a memory element electrode, a chalcogenide based memory element disposed between the memory element electrode and the heater electrode, and a control element disposed between the heater electrode and the control element electrode.

Abstract: A memory cell has a first and second conductor. The first conductor is oriented in a first direction and the second conductor is oriented in a second direction. The first conductor has at least one edge. A state-change layer is disposed on the first conductor and a control element is partially offset over the at least one edge of the first conductor. The control element is disposed between the first and second conductors. Preferably the state-change layer is a direct-tunneling or dielectric rupture anti-fuse. A memory array can be formed from a plurality of the memory cells. Optionally, creating multiple layers of the memory cells can form a three-dimensional memory array.

Abstract: A memory structure has a plurality of row conductors intersecting a plurality of column conductors at a plurality of intersections. Each intersection includes an electrically linear resistive element in series with a voltage breakdown element.

Abstract: A cubic memory array is fabricated on a substrate having a planar surface. The cubic memory array includes a plurality of first select-lines organized in more than one plane parallel to the planar surface. A plurality of second select-lines is formed in pillars disposed orthogonal to the planer surface of the substrate. A plurality of memory cells are respectively coupled to the plurality of first and plurality of second select-lines.

Abstract: A method of creating a memory circuit preferably includes (1) forming a first plurality of select-lines in a plane substantially parallel to a substrate, (2) forming a second plurality of select-lines in a plane substantially parallel to the substrate, where the second plurality of select-lines is divided into first and second groups, where the first group is formed in a direction normal to that of the first plurality of select-lines and the second group is formed in a direction substantially diagonal to that of the first group, (3) forming a plurality of pillars normal to the substrate, and (4) forming an array of memory cells, each memory cell being respectively coupled to a pillar and one of each of said first and second pluralities of select-lines.

Abstract: Interconnection structures for integrated circuits have first cells disposed in a first plane, at least second cells disposed in at least a second plane parallel to the first plane, and vertical interconnections disposed for connecting conductors in the first plane with conductors in the second plane, at least some of the vertical interconnections initially incorporating antifuses. The antifuses may be disposed over conductors that are disposed on a base substrate. The antifuses are selectively fused to prepare the integrated circuit for normal operation. Methods for fabricating and using such vertical interconnection structures are disclosed.

Abstract: An antifuse structure has an antifuse between first and second thermal conduction regions. Each of the first and second thermal conduction regions has a portion of low thermal conductivity and a portion of high thermal conductivity. The portion having low thermal conductivity is between the respective portion of high thermal conductivity and the antifuse.

Abstract: A memory structure that includes a first electrode, a second electrode, a thermal conduction limiting electrode having a thermal conductivity that is less than a thermal conductivity of the first electrode, a memory storage element disposed between the thermal conduction limiting electrode and the second electrode, and a control element disposed between the second electrode and the first electrode.

Abstract: A memory structure that includes a control element electrode, a heater electrode, a memory element electrode, a chalcogenide based memory element disposed between the memory element electrode and the heater electrode, and a control element disposed between the heater electrode and the control element electrode.

Abstract: A memory storage device includes a first and second memory cell which each have a top end and a bottom end. A first and second first dimension conductor are substantially coplanar and parallel and extend in a first dimension. The first first dimension conductor intersects the bottom end of the first memory cell and the second first dimension conductor intersects the top end of the second memory cell. A first second dimension conductor extends in a second dimension and intersects the top end of the first memory cell and a second second dimension conductor extends in the second dimension and intersects the bottom end of the second memory cell. A first third dimension conductor which extends in a third dimension is positioned between the first and second memory cell to couple the first second dimension conductor to the second second dimension conductor.

Abstract: A memory cell includes a heating component that is connected to a voltage-breakdown component. The heating component is configured to accelerate the break-down of a voltage-breakdown component. Memory structures and methods for making them are also disclosed.

Abstract: Interconnection structures for integrated circuits have a first array of cells, at least a second array of cells parallel to the first array, and interconnections disposed for connecting cells of the first array with cells of the second array, at least some of the interconnections being disposed along axes oriented obliquely to the first and second arrays. First and second sets of oblique axes of interconnections may be parallel or opposed to each other. The interconnections may include obliquely slanted pillars or stair-stepped pillars disposed along the oblique axes. Methods for fabricating and using such structures are disclosed.

Abstract: An intermesh memory device includes memory components that each have a determinable resistance value and electronic switches that each control current through one or more of the memory components such that a potential is applied to the memory components. A first electronic switch of the intermesh memory device is electrically coupled to an input of a memory component and a second electronic switch is electrically coupled to an output of the memory component. The first electronic switch and the second electronic switch are configured together to apply a potential to the memory component.