Abstract: A computer-readable medium tangibly embodying a program of machine-readable instructions executable by a digital processor of a computer system to perform operations for controlling computer system activities. The operations include receiving a command entered with an input device of the computer system to begin opportunistic computer system activities, where the command specifies a time period available for opportunistic computer system activities. Then initiating at least one computer system activity during the time period available for opportunistic computer system activities.

Abstract: A computer-readable medium tangibly embodying a program of machine-readable instructions executable by a digital processor of a computer system to perform operations for controlling computer system activities. The operations include receiving a command entered with an input device of the computer system to begin opportunistic computer system activities, where the command specifies a time period available for opportunistic computer system activities. Then initiating at least one computer system activity during the time period available for opportunistic computer system activities.

Abstract: The present invention concerns methods and apparatus for performing computer system maintenance and notification activities in an opportunistic manner during time periods identified by a user when the user expects not to be using the computer system. In methods and systems of the present invention, the user prioritizes computer system maintenance activities from high to low. When an opportunity arises to perform maintenance activities due to the user, for example, being away from the computer, the user specifies the length of time the user expects to be away from the computer using apparatus of the present invention. Methods of the present invention then initiate computer system maintenance activities beginning with the highest-priority maintenance activity that can be completed during the time period identified by the user. The method continues performing maintenance activities from highest to lowest priority for so long as there is enough time remaining to perform the next maintenance task.

Abstract: The present invention concerns methods and apparatus for performing computer system maintenance and notification activities in an opportunistic manner during time periods identified by a user when the user expects not to be using the computer system. In methods and systems of the present invention, the user prioritizes computer system maintenance activities from high to low. When an opportunity arises to perform maintenance activities due to the user, for example, being away from the computer, the user specifies the length of time the user expects to be away from the computer using apparatus of the present invention. Methods of the present invention then initiate computer system maintenance activities beginning with the highest-priority maintenance activity that can be completed during the time period identified by the user. The method continues performing maintenance activities from highest to lowest priority for so long as there is enough time remaining to perform the next maintenance task.

Abstract: A facility is provided for managing register maps for map-based indirect register file access within a processor. The management facility includes a register mapping including a set of maps, each map of the set of maps having a plurality of map registers. A set of actual registers is indirectly accessed by the processor via map entries of the set of maps. The number of actual registers in the set of actual registers is greater than the number of map entries in the set of maps, and the map entries of the set of maps reference only a subset of the set of actual registers at any given time. The facility includes managing updates to multiple entries of the set of maps of the register mapping by updating multiple map entries of at least one map of the set of maps responsive to executing a single update instruction.

Abstract: The present invention concerns methods and apparatus for performing computer system maintenance and notification activities in an opportunistic manner during time periods identified by a user when the user expects not to be using the computer system. In methods and systems of the present invention, the user prioritizes computer system maintenance activities from high to low. When an opportunity arises to perform maintenance activities due to the user, for example, being away from the computer, the user specifies the length of time the user expects to be away from the computer using apparatus of the present invention. Methods of the present invention then initiate computer system maintenance activities beginning with the highest-priority maintenance activity that can be completed during the time period identified by the user. The method continues performing maintenance activities from highest to lowest priority for so long as there is enough time remaining to perform the next maintenance task.

Abstract: A facility is provided for managing register maps for map-based indirect register file access within a processor. The management facility includes a register mapping including a set of maps, each map of the set of maps having a plurality of map registers. A set of actual registers is indirectly accessed by the processor via map entries of the set of maps. The number of actual registers in the set of actual registers is greater than the number of map entries in the set of maps, and the map entries of the set of maps reference only a subset of the set of actual registers at any given time. The facility includes managing updates to multiple entries of the set of maps of the register mapping by updating multiple map entries of at least one map of the set of maps responsive to executing a single update instruction.

Abstract: A facility is provided for managing register maps for map-based indirect register file access within a processor. The management facility includes a register mapping including a set of maps, each map of the set of maps having a plurality of map registers. A set of actual registers is indirectly accessed by the processor via map entries of the set of maps. The number of actual registers in the set of actual registers is greater than the number of map entries in the set of maps, and the map entries of the set of maps reference only a subset of the set of actual registers at any given time. The facility includes managing updates to multiple entries of the set of maps of the register mapping by updating multiple map entries of at least one map of the set of maps responsive to executing a single update instruction.

Abstract: A method for providing a service for a traveler to acquire at least one item at the traveler's destination, comprising the steps of receiving a request from a traveler for obtaining at least one item; providing the traveler with the option to one of rent and purchase the at least one item, arranging for the at least one item to be supplied, arranging for shipping of the at least one item to a location selected by the traveler at a time selected by the traveler; and conducting a transaction with the traveler for obtaining the at least one item.

Abstract: A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.

Abstract: A method and system for attached processing units accessing a shared memory in an SMT system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.

Abstract: A method and system for attached processing units accessing a shared memory in an SMT system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.

Abstract: A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.

Abstract: A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.

Abstract: A system to facilitate electronic shopping operates to associate a set of items with an activity, and, in response to a consumer selection of the activity, to associate the set of items with an electronic shopping cart. According to other aspects, an indication of an activity is transmitted to a consumer, a consumer selection of the activity is received, and, in response to the consumer selection, a set of items is associated with an electronic shopping cart. In still further aspects, an electronic shopping cart is provided, a set of items is associated with an activity, a consumer selection of the activity is received, and, in response to the consumer selection, the set of items is associated with the electronic shopping cart.

Abstract: A system, method, apparatus, means, and computer program code for creating and using an order for a product (e.g., a good and/or a service) that has a non-binding attribute such that different configurations of the product are possible that will satisfy the order. A non-binding attribute may allow more than one component to be used to build a product, each of which provides a level of functionality or capability acceptable to the customer. Thus, different components may result in different product configurations. A company manufacturing the product in accordance with the order may wait until building the product to determine which configuration to use.

Abstract: A method for providing a service for a traveler to acquire at least one item at the traveler's destination, comprising the steps of receiving a request from a traveler for obtaining at least one item; providing the traveler with the option to one of rent and purchase the at least one item, arranging for the at least one item to be supplied, arranging for shipping of the at least one item to a location selected by the traveler at a time selected by the traveler; and conducting a transaction with the traveler for obtaining the at least one item.

Abstract: A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.

Abstract: Methods, systems and computer program products are provided for providing information in the form of an insertion to a user during delays in retrieving program material with an interactive system. This may include making a determination of whether the delay is going to be sufficiently long to provide the user with an insertion. In addition, the insertion may be customized to either the user or to the program material requested, or to both the user and the requested program material. The insertion may include control logic that provides the user with control over the insertion and/or the interactive system.

Abstract: A warning timer adapted for use in an interactive data processing system which generates an alarm when a user receives output at an input/output device when he or she is not likely to be paying attention to the input/output device. The user is assumed to be paying attention for a specified amount of time after he or she last sent a request to a computer or received a response from the computer. The specified amount of time corresponds to the length of the user's attention span. The warning timer operates as follows. When the user receives a response, it calculates the amount of time that has elapsed since the user last sent a request or received a response. If the elapsed time exceeds the specified amount of time, it generates an alarm to alert the user.