Patents by Inventor Peter G. Tolchinsky

Peter G. Tolchinsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190279908
    Abstract: Techniques are disclosed for monolithic co-integration of silicon (Si)-based transistor devices and III-N semiconductor-based transistor devices over a commonly shared semiconductor substrate. In accordance with some embodiments, the disclosed techniques may be used to provide a silicon-on-insulator (SOI) or other semiconductor-on-insulator structure including: (1) a Si (111) surface available for formation of III-N-based n-channel devices; and (2) a Si (100) surface available for formation of Si-based p-channel devices, n-channel devices, or both. Further processing may be performed, in accordance with some embodiments, to provide n-channel and p-channel devices over the Si (111) and Si (100) surfaces, as desired.
    Type: Application
    Filed: June 22, 2016
    Publication date: September 12, 2019
    Applicant: INTEL CORPORATION
    Inventors: MARKO RADOSAVLJEVIC, HAN WUI THEN, SANSAPTAK DASGUPTA, PETER G. TOLCHINSKY
  • Publication number: 20190051650
    Abstract: This disclosure pertains to a gallium nitride transistor that is formed in a trench etched into a silicon substrate. A gallium nitride layer is on the trench of the silicon substrate. A source electrode and a drain electrode reside on the gallium nitride layer. A gate electrode resides on the gallium nitride layer between the source electrode and the drain electrode. A first polarization layer resides on the gallium nitride layer between the source electrode and the gate electrode, and a second polarization layer resides on the gallium nitride layer between the gate electrode and the drain electrode. The silicon substrate can include a silicon 111 substrate.
    Type: Application
    Filed: March 28, 2016
    Publication date: February 14, 2019
    Applicant: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Peter G. Tolchinsky, Roza Kotlyar, Valluri R. Rao
  • Publication number: 20180145052
    Abstract: GaN-On-Silicon (GOS) structures and techniques for accommodating and/or controlling stress/strain incurred during III-N growth on a large diameter silicon substrate. A back-side of a silicon substrate may be processed to adapt substrates of standardized diameters and thicknesses to GOS applications. Bowing and/or warping during high temperature epitaxial growth processes may be mitigated by pre-processing silicon substrate so as to pre-stress the substrate in a manner than counterbalances stress induced by the III-N material and/or improve a substrate's ability to absorb stress. III-N devices fabricated on an engineered GOS substrate may be integrated together with silicon MOS devices fabricated on a separate substrate. Structures employed to improve substrate resilience and/or counterbalance the substrate stress induced by the III-N material may be further employed for interconnecting the III-N and silicon MOS devices of a 3D IC.
    Type: Application
    Filed: June 26, 2015
    Publication date: May 24, 2018
    Inventors: Sansaptak DASGUPTA, Han Wui THEN, Marko RADOSAVLJEVIC, Peter G. TOLCHINSKY, Robert S. CHAU
  • Patent number: 9711591
    Abstract: Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the devices formed thereby are described. In one embodiment, the method includes providing a substrate having a top surface with a lattice constant and depositing a first layer on the top surface of the substrate. The first layer has a top surface with a lattice constant that is different from the first lattice constant of the top surface of the substrate. The first layer is annealed and polished to form a polished surface. A second layer is then deposited above the polished surface.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: July 18, 2017
    Assignee: Intel Corporation
    Inventors: Niloy Mukherjee, Matthew V. Metz, James M. Powers, Van H. Le, Benjamin Chu-Kung, Mark R. Lemay, Marko Radosavljevic, Niti Goel, Loren Chow, Peter G. Tolchinsky, Jack T. Kavalieros, Robert S. Chau
  • Patent number: 9691843
    Abstract: Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate. The first nanowire or semiconductor body is composed of a semiconductor material having a first global crystal orientation. The semiconductor structure also includes a second semiconductor device having a second nanowire or semiconductor body disposed above the crystalline substrate. The second nanowire or semiconductor body is composed of a semiconductor material having a second global crystal orientation different from the first global orientation. The second nanowire or semiconductor body is isolated from the crystalline substrate by an isolation pedestal disposed between the second nanowire or semiconductor body and the crystalline substrate.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Peter G. Tolchinsky, Kelin J. Kuhn, Glenn A. Glass, Van H. Le
  • Patent number: 9559160
    Abstract: Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate. The first nanowire or semiconductor body is composed of a semiconductor material having a first global crystal orientation. The semiconductor structure also includes a second semiconductor device having a second nanowire or semiconductor body disposed above the crystalline substrate. The second nanowire or semiconductor body is composed of a semiconductor material having a second global crystal orientation different from the first global orientation. The second nanowire or semiconductor body is isolated from the crystalline substrate by an isolation pedestal disposed between the second nanowire or semiconductor body and the crystalline substrate.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: January 31, 2017
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Peter G. Tolchinsky, Kelin J. Kuhn, Glenn A. Glass, Van H. Le
  • Publication number: 20160133735
    Abstract: Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate. The first nanowire or semiconductor body is composed of a semiconductor material having a first global crystal orientation. The semiconductor structure also includes a second semiconductor device having a second nanowire or semiconductor body disposed above the crystalline substrate. The second nanowire or semiconductor body is composed of a semiconductor material having a second global crystal orientation different from the first global orientation. The second nanowire or semiconductor body is isolated from the crystalline substrate by an isolation pedestal disposed between the second nanowire or semiconductor body and the crystalline substrate.
    Type: Application
    Filed: January 14, 2016
    Publication date: May 12, 2016
    Inventors: Annalisa CAPPELLANI, Peter G. TOLCHINSKY, Kelin J. KUHN, Glenn A. GLASS, Van H. LE
  • Patent number: 8617945
    Abstract: A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm?2 to be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: December 31, 2013
    Assignee: Intel Corporation
    Inventors: Mantu K. Hudait, Mohamad A. Shaheen, Loren A. Chow, Peter G. Tolchinsky, Joel M. Fastenau, Dmitri Loubychev, Amy W. K. Liu
  • Publication number: 20130320294
    Abstract: Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate. The first nanowire or semiconductor body is composed of a semiconductor material having a first global crystal orientation. The semiconductor structure also includes a second semiconductor device having a second nanowire or semiconductor body disposed above the crystalline substrate. The second nanowire or semiconductor body is composed of a semiconductor material having a second global crystal orientation different from the first global orientation. The second nanowire or semiconductor body is isolated from the crystalline substrate by an isolation pedestal disposed between the second nanowire or semiconductor body and the crystalline substrate.
    Type: Application
    Filed: December 23, 2011
    Publication date: December 5, 2013
    Inventors: Annalisa Cappellani, Peter G. Tolchinsky, Kelin J. Kuhn, Glenn A. Glass, Van H. Le
  • Patent number: 8217383
    Abstract: The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium (“Ge”) transistor structure on a Silicon (“Si”) substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: July 10, 2012
    Assignee: Intel Corporation
    Inventors: Mantu K. Hudait, Suman Datta, Jack T. Kavalieros, Peter G. Tolchinsky
  • Publication number: 20120142166
    Abstract: A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108cm?2 to be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.
    Type: Application
    Filed: February 3, 2012
    Publication date: June 7, 2012
    Inventors: Mantu K. Hudait, Mohamad A. Shaheen, Loren A. Chow, Peter G. Tolchinsky, Joel M. Fastenau, Dmitri Loubychev, Amy W.K. Liu
  • Patent number: 8143646
    Abstract: A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm?2 to be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: March 27, 2012
    Assignee: Intel Corporation
    Inventors: Mantu K. Hudait, Mohamad A. Shaheen, Loren A. Chow, Peter G. Tolchinsky, Joel M. Fastenau, Dmitri Loubychev, Amy W. K. Liu
  • Patent number: 7863710
    Abstract: Dislocation removal from a group III-V film grown on a semiconductor substrate is generally described. In one example, an apparatus includes a semiconductor substrate, a buffer film including a group III-V semiconductor material epitaxially coupled to the semiconductor substrate wherein the buffer film includes material melted by laser pulse irradiation and recrystallized to substantially remove dislocations or defects from the buffer film, and a first semiconductor film epitaxially grown on the buffer film wherein a lattice mismatch exists between the semiconductor substrate and the first semiconductor film.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: January 4, 2011
    Assignee: Intel Corporation
    Inventors: Mantu K. Hudait, Peter G. Tolchinsky, Jack T. Kavalieros, Marko Radosavljevic
  • Publication number: 20100327261
    Abstract: The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium (“Ge”) transistor structure on a Silicon (“Si”) substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
    Type: Application
    Filed: September 7, 2010
    Publication date: December 30, 2010
    Applicant: INTEL CORPORATION
    Inventors: Mantu K. Hudait, Suman Datta, Jack T. Kavalieros, Peter G. Tolchinsky
  • Patent number: 7851781
    Abstract: Various embodiments provide a buffer layer that is grown over a silicon substrate that provides desirable device isolation for devices formed relative to III-V material device layers, such as InSb-based devices, as well as bulk thin film grown on a silicon substrate. In addition, the buffer layer can mitigate parallel conduction issues between transistor devices and the silicon substrate. In addition, the buffer layer addresses and mitigates lattice mismatches between the film relative to which the transistor is formed and the silicon substrate.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: December 14, 2010
    Assignee: Intel Corporation
    Inventors: Mantu K. Hudait, Mohamad A. Shaheen, Loren A. Chow, Peter G. Tolchinsky, Joel M. Fastenau, Dmitri Loubychev, Amy W. K. Liu
  • Patent number: 7791063
    Abstract: The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium (“Ge”) transistor structure on a Silicon (“Si”) substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: September 7, 2010
    Assignee: Intel Corporation
    Inventors: Mantu K. Hudait, Suman Datta, Jack T. Kavalieros, Peter G. Tolchinsky
  • Publication number: 20100155880
    Abstract: A silicon-on-insulator (SOI) substrate comprises a base silicon substrate having a back gate region, wherein the back gate region has a first dopant concentration that is greater than 1×1017 cm?3, a nitrogen layer adjacent to the back gate region of the base silicon substrate, a BOX layer adjacent to the nitrogen layer, and a thin silicon device layer adjacent to the BOX layer, wherein the thin silicon device layer has a first dopant concentration that is less than 1×1017 cm?3. In some implementations, the thin silicon device layer has a first dopant concentration that is less than 1×1015 cm?3.
    Type: Application
    Filed: December 23, 2008
    Publication date: June 24, 2010
    Inventors: Ibrahim Ban, Peter G. Tolchinsky, Irwin Yablok
  • Publication number: 20100148153
    Abstract: A group III-V material device has a delta-doped region below a channel region. This may improve the performance of the device by reducing the distance between the gate and the channel region.
    Type: Application
    Filed: December 16, 2008
    Publication date: June 17, 2010
    Inventors: Mantu K. Hudait, Peter G. Tolchinsky, Robert S. Chau, Marko Radosavljevic, Ravi Pillarisetty, Aaron A. Budrevich
  • Patent number: 7687799
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a GaSb nucleation layer on a substrate, forming a Ga(Al)AsSb buffer layer on the GaSb nucleation layer, forming an In0.52Al0.48As bottom barrier layer on the Ga(Al)AsSb buffer layer, and forming a graded InxAl1-xAs layer on the In0.52Al0.48As bottom barrier layer thus enabling the fabrication of low defect, device grade InGaAs based quantum well structures.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: March 30, 2010
    Assignee: Intel Corporation
    Inventors: Mantu K. Hudait, Peter G. Tolchinsky, Loren A. Chow, Dmitri Loubychev, Joel M. Fastenau, Amy W. K. Liu
  • Publication number: 20090315018
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a GaSb nucleation layer on a substrate, forming a Ga(Al)AsSb buffer layer on the GaSb nucleation layer, forming an In0.52Al0.48As bottom barrier layer on the Ga(Al)AsSb buffer layer, and forming a graded InxAl1-xAs layer on the In0.52Al0.48As bottom barrier layer thus enabling the fabrication of low defect, device grade InGaAs based quantum well structures.
    Type: Application
    Filed: June 19, 2008
    Publication date: December 24, 2009
    Inventors: Mantu K. Hudait, Peter G. Tolchinsky, Loren A. Chow, Dmitri Loubychev, Joel M. Fastenau, Amy W.K. Liu