Patents by Inventor Peter G. Vavaroutsos
Peter G. Vavaroutsos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10402022Abstract: A capacitive sensor array may include a first set of sensor electrodes and a second set of sensor electrodes. Each of the second set of sensor electrodes may intersect each of the first set of sensor electrodes to form a plurality of unit cells each corresponding to a pair of sensor electrodes including one of the first set of sensor electrodes and one of the second set of sensor electrodes. Each point within each of the plurality of unit cells may nearer to a gap between the pair of sensor electrodes corresponding to the unit cell than to a gap between any different pair of sensor electrodes, and a first trace pattern within a first unit cell of the plurality of unit cells may be different from a second trace pattern within an adjacent unit cell of the plurality of unit cells.Type: GrantFiled: March 1, 2017Date of Patent: September 3, 2019Assignee: Cypress Semiconductor CorporationInventors: Massoud Badaye, Peter G Vavaroutsos, Milton D. A. Ribeiro, Oleksandr Hoshtanar
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Publication number: 20170262094Abstract: A capacitive sensor array may include a first set of sensor electrodes and a second set of sensor electrodes. Each of the second set of sensor electrodes may intersect each of the first set of sensor electrodes to form a plurality of unit cells each corresponding to a pair of sensor electrodes including one of the first set of sensor electrodes and one of the second set of sensor electrodes. Each point within each of the plurality of unit cells may nearer to a gap between the pair of sensor electrodes corresponding to the unit cell than to a gap between any different pair of sensor electrodes, and a first trace pattern within a first unit cell of the plurality of unit cells may be different from a second trace pattern within an adjacent unit cell of the plurality of unit cells.Type: ApplicationFiled: March 1, 2017Publication date: September 14, 2017Applicant: Cypress Semiconductor CorporationInventors: Massoud Badaye, Peter G Vavaroutsos, Milton D.A. Ribeiro, Oleksandr Hoshtanar
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Publication number: 20160154507Abstract: Disclosed herein are systems, methods, and devices for touch event and hover event detection. Devices as disclosed herein may include a first electrode implemented in a capacitive sensor. The devices may also include a second electrode implemented in the capacitive sensor. The devices may further include a controller coupled to the first electrode and the second electrode, where the controller is configured to determine whether a touch event or a hover event has occurred based on a first self-capacitance measurement of the first electrode, a second self-capacitance measurement of the second electrode, and a mutual capacitance measurement of the first electrode and the second electrode.Type: ApplicationFiled: May 15, 2015Publication date: June 2, 2016Applicant: Cypress Semiconductor CorporationInventors: Vibheesh Bharathan, Peter G. Vavaroutsos, Jinghui Mu
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Publication number: 20140210784Abstract: Described herein are capacitance sensing devices and methods for forming such devices. A capacitance sensing device includes a substrate and a plurality of electrodes disposed on an area of the substrate to form an active portion of the device. Each of the plurality of electrodes comprises at least one irregular edge formed along a non-linear path. The touch sensor also includes a first plurality of conductors disposed on the substrate. Each of the first plurality of conductors has an end electrically connected to one of the plurality of electrodes. The touch sensor can also include a second plurality of conductors that form a routing channel. Each of the second plurality of conductors has an end electrically connected to a second end of one of the first plurality of conductors. Each of the second plurality of conductors has an end electrically connected to a second end of one of the first plurality of conductors.Type: ApplicationFiled: March 28, 2014Publication date: July 31, 2014Applicant: Cypress Semiconductor CorporationInventors: Alexandre Gourevitch, Peter G. Vavaroutsos, Vikas R. Dhurka
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Patent number: 8484838Abstract: Embodiments for constructing capacitance sensing devices include, but are not limited to, forming a plurality of electrodes on a central portion of a substrate, the substrate comprising a central portion and an outer portion, forming a first plurality of conductors on the substrate, each of the first plurality of conductors being connected to and extending from at least one of the plurality of electrodes, and forming an insulating material on the outer portion of the substrate and at least partially over some of the first plurality of conductors. The constructing also includes forming a second plurality of conductors on the insulating material, wherein the second plurality of conductors and the insulating material are configured such that each of the second plurality of conductors is electrically connected to at least some of the first plurality of conductors and is insulated from the others of the first plurality of conductors.Type: GrantFiled: June 20, 2012Date of Patent: July 16, 2013Assignee: Cypress Semiconductor CorporationInventors: Massoud Badaye, Peter G. Vavaroutsos, John Carey, Patrick Prendergast
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Publication number: 20120256642Abstract: Embodiments described herein provide capacitance sensing devices and methods for forming such devices. The capacitance sensing devices include a substrate having a central and an outer portion. A plurality of substantially co-planar electrodes are on the central portion substrate. A first plurality of conductors are on the substrate. Each of the first plurality of conductors has a first end portion electrically connected to one of the plurality of electrodes and a second end portion on the outer portion of the substrate. An insulating material is coupled to the second end portions of the first plurality of conductors. A second plurality of conductors are coupled to the insulating material. Each of the second plurality of conductors is electrically connected to the second end portion of at least some of the first plurality of conductors and is insulated from the second end portion of the others of the first plurality of conductors.Type: ApplicationFiled: June 20, 2012Publication date: October 11, 2012Applicant: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Massoud Badaye, Peter G. Vavaroutsos, John Carey, Patrick Prendergast
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Patent number: 5455934Abstract: The disk array control system is a fault tolerant controller for arrays of hard disk drives. With the controller as a front end, an array of hard disk drives would appear as a single drive to a host computer system connected to the controller. The controller translates input/output data transfer requests from the host system to input/output data transfer requests for the appropriate drives in the drive array. To minimize latency, translation techniques provide for a minimal number of accesses to the drives in the array. Queued input/output requests are supported, and, to maximize throughput, optimal scheduling techniques are used to optimize resource usage and minimize drive access overheads. Means are provided for detecting module failures, sustaining operation after failure, and replacing faulty modules without interrupting service.Type: GrantFiled: March 11, 1994Date of Patent: October 3, 1995Assignee: Eclipse Technologies, Inc.Inventors: Alexander Holland, Peter G. Vavaroutsos
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Patent number: 5367669Abstract: The disk array control system is a fault tolerant controller for arrays of hard disk drives. With the controller as a front end, an array of hard disk drives would appear as a single drive to a host computer system connected to the controller. The controller translates input/output data transfer requests from the host system to input/output data transfer requests for the appropriate drives in the drive array. To minimize latency, translation techniques provide for a minimal number of accesses to the drives in the array. Queued input/output requests are supported, and, to maximize throughput, optimal scheduling techniques are used to optimize resource usage and minimize drive access overheads. Means are provided for detecting module failures, sustaining operation after failure, and replacing faulty modules without interrupting service.Type: GrantFiled: March 23, 1993Date of Patent: November 22, 1994Assignee: Eclipse Technologies, Inc.Inventors: Alexander Holland, Peter G. Vavaroutsos