Patents by Inventor Peter Gansauge

Peter Gansauge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5244833
    Abstract: A method for making an integrated circuit chip packaging structure comprising a substrate, preferably a semiconductor base substrate, a conductive layer on said substrate in regions where connections to metallization layers of the substrate are formed, solder balls and gold bumps connected to said conductive layer in said regions of said conductive layer, and a solder stop layer on said conductive layer at least around said solder balls. The conductive layer further comprises wiring lines. Further, a method of forming the structure is disclosed which uses only two masks for providing terminals for connecting the substrate to integrated circuits and to other substrates or to the printed circuit board and wiring lines. Thus, there is a need for one less metallization layer. The method is applicable to 200 mm wafers and allows two different packaging technologies (C-4 and TAB or wire-bonding) on the same substrate. Thus, packaging of VLSI circuits is improved.
    Type: Grant
    Filed: April 11, 1991
    Date of Patent: September 14, 1993
    Assignee: International Business Machines Corporation
    Inventors: Peter Gansauge, Volker Kreuter, Helmut Schettler
  • Patent number: 5010389
    Abstract: An integrated circuit chip packaging structure comprising a substrate, preferably a semiconductor base substrate, a conductive layer on said substrate in regions where connections to metallization layers of the substrate are formed, solder balls and gold bumps connected to said conductive layer in said regions of said conductive layer, and a solder stop layer on said conductive layer at least around said solder balls. The conductive layer, further comprises wiring lines. Further, a method of forming the structure is disclosed which uses only two masks for providing terminals for connecting the substrate to integrated circuits and to other substrates or to the printed circuit board and wiring lines. Thus, there is a need for one less metallization layer. The method is applicable to 200 mm wafers and allows two different packaging technologies (C-4 and TAB or wire-bonding) on the same substrate. Thus, packaging of VLSI circuits is improved.
    Type: Grant
    Filed: May 29, 1990
    Date of Patent: April 23, 1991
    Assignee: International Business Machines Corporation
    Inventors: Peter Gansauge, Volker Kreuter, Helmut Schettler
  • Patent number: 3960605
    Abstract: A method of ion implantation, in which boron ions are generated by introducing a boron-oxide containing material vapor into a conventional gas discharge ion generation source.
    Type: Grant
    Filed: January 23, 1975
    Date of Patent: June 1, 1976
    Assignee: International Business Machines Corporation
    Inventors: Siegfried Beck, Karl Brack, Peter Gansauge