Abstract: The present invention provides a field programmable network application specific integrated circuit and a method of operation thereof. In one advantageous embodiment, the field programmable network application specific integrated circuit includes a media access controller and a programmable logic core having an array of dynamically configurable arithmetic logic units. The programmable logic core configured to interface with the media access controller and implement at least one application level function capable of generating meta-data. The media access controller and the programmable logic controller form at least a portion of a MP-block.

Abstract: The present invention provides an application specific integrated circuit and a method of operation thereof. In one advantageous embodiment, the application specific integrated circuit includes a programmable logic core having an array of dynamically configurable arithmetic logic units. This particular embodiment further includes a network interface subsystem that includes a media access controller. The network interface is configured to employ a first portion of the programmable logic core that interfaces with the media access controller and that is configurable to process control data. This embodiment further includes a data transmission subsystem associated with a memory device, and configured to employ a second portion of the programmable logic core that stores received data from the network interface subsystem to the memory device and sends transmission data from the memory device to the network interface subsystem in response to an instruction from a host system.

Abstract: The present invention provides a field programmable universal serial bus application specific integrated circuit and a method of operation thereof. In one advantageous embodiment, the field programmable universal serial bus application specific integrated circuit includes a universal serial bus function core configured to transmit and receive data via a universal serial bus and a programmable logic core having an array of dynamically configurable arithmetic logic units. The programmable logic core is configured to interface with the universal serial bus function core and implement at least one application level function capable of performing protocol conversion to at least one processor bus protocol.