Patents by Inventor Peter Geens

Peter Geens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory device with reduced standby power consumption and method for operating same
    Patent number: 7751270
    Abstract: Disclosed herein are memory devices comprising a plurality of memory cells to which a standby voltage is to be supplied during standby mode to avoid loss of data, and methods of operating said memory devices, the methods comprising: (a) determining an actual value of a bit integrity parameter of the memory cells; (b) comparing said actual value with a predetermined minimal value of the bit integrity parameter which takes into account possible variations in cell properties as a result of process variations; and (c) adjusting the standby voltage towards a more optimal value based on the result of the comparison in such a way that said bit integrity parameter determined for said more optimal value of the standby voltage approaches the predetermined minimal value. The circuitry for measuring the bit integrity parameter preferably comprises a plurality of replica test cells which are added to the memory matrix.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: July 6, 2010
    Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&D
    Inventors: Peter Geens, Wim Dehaene
  • Memory Device with Reduced Standby Power Consumption and Method for Operating Same
    Publication number: 20080219080
    Abstract: Disclosed herein are memory devices comprising a plurality of memory cells to which a standby voltage is to be supplied during standby mode to avoid loss of data, and methods of operating said memory devices, the methods comprising: (a) determining an actual value of a bit integrity parameter of the memory cells; (b) comparing said actual value with a predetermined minimal value of the bit integrity parameter which takes into account possible variations in cell properties as a result of process variations; and (c) adjusting the standby voltage towards a more optimal value based on the result of the comparison in such a way that said bit integrity parameter determined for said more optimal value of the standby voltage approaches the predetermined minimal value. The circuitry for measuring the bit integrity parameter preferably comprises a plurality of replica test cells which are added to the memory matrix.
    Type: Application
    Filed: January 25, 2008
    Publication date: September 11, 2008
    Applicants: Interuniversitair Microelektronica Centrum (IMEC), Katholieke Universiteit Leuven
    Inventors: Peter Geens, Wim Dehaene