Patents by Inventor Peter Gene Sassone

Peter Gene Sassone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9715392
    Abstract: A method includes identifying, at a scheduling unit, a resource conflict at a shared processing resource that is accessible by a first processing cluster and by a second processing cluster, where the first processing cluster, the second processing cluster, and the shared processing resource are included in a very long instruction word (VLIW) processing unit. The method also includes resolving the resource conflict.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: July 25, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Suresh Kumar Venkumahanti, Ankit Ghiya, Peter Gene Sassone, Lucian Codrescu, Suman Mamidi
  • Patent number: 9552033
    Abstract: Latency-based power mode units for controlling power modes of processor cores, and related methods and systems are disclosed. In one aspect, the power mode units are configured to reduce power provided to the processor core when the processor core has one or more threads in pending status and no threads in active status. An operand of an instruction being processed by a thread may be data in memory located outside processor core. If the processor core does not require as much power to operate while a thread waits for a request from outside the processor core, the power consumed by the processor core can be reduced during these waiting periods. Power can be conserved in the processor core even when threads are being processed if the only threads being processed are in pending status, and can reduce the overall power consumption in the processor core and its corresponding CPU.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: January 24, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Suresh Kumar Venkumahanti, Peter Gene Sassone, Sanjay Bhagawan Patil
  • Publication number: 20160062770
    Abstract: A method includes identifying, at a scheduling unit, a resource conflict at a shared processing resource that is accessible by a first processing cluster and by a second processing cluster, where the first processing cluster, the second processing cluster, and the shared processing resource are included in a very long instruction word (VLIW) processing unit. The method also includes resolving the resource conflict.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 3, 2016
    Inventors: Suresh Kumar Venkumahanti, Ankit Ghiya, Peter Gene Sassone, Lucian Codrescu, Suman Mamidi
  • Publication number: 20150301573
    Abstract: Latency-based power mode units for controlling power modes of processor cores, and related methods and systems are disclosed. In one aspect, the power mode units are configured to reduce power provided to the processor core when the processor core has one or more threads in pending status and no threads in active status. An operand of an instruction being processed by a thread may be data in memory located outside processor core. If the processor core does not require as much power to operate while a thread waits for a request from outside the processor core, the power consumed by the processor core can be reduced during these waiting periods. Power can be conserved in the processor core even when threads are being processed if the only threads being processed are in pending status, and can reduce the overall power consumption in the processor core and its corresponding CPU.
    Type: Application
    Filed: April 22, 2014
    Publication date: October 22, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Suresh Kumar Venkumahanti, Peter Gene Sassone, Sanjay Bhagawan Patil