Abstract: Variable width error correction is described. A memory controller can determine, from a memory address, what type of error correction is to be applied for the address region of that memory address and can generate commands for the memory device. An amount of error correction metadata associated with that address region may vary depending on the spatial location of the address region. In some cases, two translations may be performed: one by a processor using information set up by an operating system and another by the memory controller (or the memory device). In other cases, a single translation may be performed, for example by a processor using information set up by the operating system, which can determine the variable error correction during translation of a virtual address region to a real physical address region.

Abstract: Electrical battery apparatus embodiments are presented that generally involve incorporating sensing, computing, and communication capabilities into the one common component that a vast number of electronic devices employ—namely batteries. By integrating these capabilities into disposable and/or rechargeable batteries, new functionality and intelligence can be provided to otherwise stand-alone devices.

Abstract: An aggregation framework system and method that automatic configures, aggregates, disaggregates, manages, and optimizes components of a consolidated system of devices, modules, and sensors. Embodiments of the system and method include a low-power alert sensor, a data aggregator module, and an interpreter module. The low-power alert sensor is a sensor that is continuously on and continuously monitoring its environment. The low-power alert sensor acts as a watchdog and triggers other sensors to awaken them from a power-conservation state when there is a change or event that occurs in an environment. The data aggregator module manages the set of sensors within the system and aggregates sensor data obtained from the sensors. The interpreter module then translates the physical data collected by sensors into logical information. Together the data aggregator module and the interpreter module present a unified logical view of the capabilities of the sensors under their control.

Abstract: Variable width error correction is described. A memory controller can determine, from a memory address, what type of error correction is to be applied for the address region of that memory address and can generate commands for the memory device. An amount of error correction metadata associated with that address region may vary depending on the spatial location of the address region. In some cases, two translations may be performed: one by a processor using information set up by an operating system and another by the memory controller (or the memory device). In other cases, a single translation may be performed, for example by a processor using information set up by the operating system, which can determine the variable error correction during translation of a virtual address region to a real physical address region.

Abstract: Electrical battery apparatus embodiments are presented that generally involve incorporating sensing, computing, and communication capabilities into the one common component that a vast number of electronic devices employ—namely batteries. By integrating these capabilities into disposable and/or rechargeable batteries, new functionality and intelligence can be provided to otherwise stand-alone devices.

Abstract: An aggregation framework system and method that automatic configures, aggregates, disaggregates, manages, and optimizes components of a consolidated system of devices, modules, and sensors. Embodiments of the system and method include a low-power alert sensor, a data aggregator module, and an interpreter module. The low-power alert sensor is a sensor that is continuously on and continuously monitoring its environment. The low-power alert sensor acts as a watchdog and triggers other sensors to awaken them from a power-conservation state when there is a change or event that occurs in an environment. The data aggregator module manages the set of sensors within the system and aggregates sensor data obtained from the sensors. The interpreter module then translates the physical data collected by sensors into logical information. Together the data aggregator module and the interpreter module present a unified logical view of the capabilities of the sensors under their control.

Abstract: The present disclosure provides methods and systems adapted for use with a processor having one or more physical cores. The methods and systems include a virtual core management component adapted to map one or more virtual cores to at least one of the physical cores to enable execution of one or more programs by the at least one physical core. The one or more virtual cores include one or more logical states associated with the execution of the one or more programs. The methods and systems may include a memory component adapted to store the one or more virtual cores. The virtual core management component may be adapted to transfer the one or more virtual cores from the memory component to the at least one physical core.

Abstract: Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein.

Abstract: Small and power-efficient buffer/mini-cache sources and sinks selected DMA accesses directed to a memory space included in a coherency domain of a microprocessor when cached data in the microprocessor is inaccessible due to any or all of the microprocessor being in a low-power state not supporting snooping. Satisfying the selected DMA accesses via the buffer/mini-cache enables reduced power consumption by allowing the microprocessor (or portion thereof) to remain in the low-power state. The buffer/mini-cache may be operated (temporarily) incoherently with respect to the cached data in the microprocessor and flushed before deactivation to synchronize with the cached data when the microprocessor (or portion thereof) transitions to a high-power state that enables snooping. Alternatively the buffer/mini-cache may be operated in a manner (incrementally) coherent with the cached data.

Abstract: A small and power-efficient buffer/mini-cache sources and sinks selected DMA accesses directed to a memory space included in a coherency domain of a microprocessor when cached data in the microprocessor is inaccessible due to any or all of the microprocessor being in a low-power state not supporting snooping. Satisfying the selected DMA accesses via the buffer/mini-cache enables reduced power consumption by allowing the microprocessor (or portion thereof) to remain in the low-power state. The buffer/mini-cache may be operated (temporarily) incoherently with respect to the cached data in the microprocessor and flushed before deactivation to synchronize with the cached data when the microprocessor (or portion thereof) transitions to a high-power state that enables snooping. Alternatively the buffer/mini-cache may be operated in a manner (incrementally) coherent with the cached data.

Abstract: Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein.