Abstract: Devices and techniques for amplifying a signal are disclosed. For instance, an amplifier includes an input node and an output node; a first gain segment including: a first transistor, where a gate of the first transistor is coupled to the input node, a first terminal of the first transistor is coupled to a ground, and a second terminal of the first transistor is coupled to the output node; a second gain segment including: a second transistor, where a gate of the second transistor is coupled to the input node, a first terminal of the second transistor is coupled to the ground, and a second terminal of the second transistor is coupled to the output node, where the first gain segment and the second gain segment are arranged in parallel with respect to the output node; and a bias circuit.

Abstract: Certain aspects of the present disclosure are directed to a memory cell implemented using front and back gate regions. One example memory cell generally includes a first semiconductor region, a second semiconductor region, and a third semiconductor region, the second semiconductor region being disposed between the first semiconductor region and the third semiconductor region. The memory cell may also include a front gate region disposed above the second semiconductor region, a floating back gate region, a first portion of the floating back gate region being disposed below the second semiconductor region, and a non-insulative region disposed adjacent to the floating back gate region.

Abstract: Certain aspects of the present disclosure are directed to a memory cell implemented using front and back gate regions. One example memory cell generally includes a first semiconductor region, a second semiconductor region, and a third semiconductor region, the second semiconductor region being disposed between the first semiconductor region and the third semiconductor region. The memory cell may also include a front gate region disposed above the second semiconductor region, a floating back gate region, a first portion of the floating back gate region being disposed below the second semiconductor region, and a non-insulative region disposed adjacent to the floating back gate region.

Abstract: A Bipolar Junction Transistor (BJT) comprises an emitter, a collector, and a base between the emitter and the collector. The BJT also comprises an emitter contact on a first side of the BJT, a base contact on the first side of the BJT, and a collector contact on a second side of the BJT. The BJT further comprises a Deep Trench Isolation (DTI) region extending from the first side of the BJT to the second side of the BJT.

Abstract: A Bipolar Junction Transistor (BJT) comprises an emitter, a collector, and a base between the emitter and the collector. The BJT also comprises an emitter contact on a first side of the BJT, a base contact on the first side of the BJT, and a collector contact on a second side of the BJT. The BJT further comprises a Deep Trench Isolation (DTI) region extending from the first side of the BJT to the second side of the BJT.

Abstract: In certain aspects, a silicon-on-insulator device comprises a back insulating layer and a semiconductor layer on the back insulating layer. The semiconductor layer includes a source region of a first conductive type having a front source surface and a back source surface, a channel region of a second conductive type have a front channel surface and a back channel surface, and a drain region of the first conductive type. The silicon-on-insulator device further comprises a gate insulating layer on the front channel surface of the channel region and a back silicidation layer on at least a portion of the back source surface and a portion of back channel surface.

Abstract: A resistor may include a semiconductor layer having a source region, a drain region, and a channel region. The channel region may be between the source region and the drain region. The channel region may have a same polarity as the source region and the drain region. The resistor may further include a first inter-metal dielectric (IMD) layer on the channel region. The resistor may further include a front-side gate shield on the first IMD layer. The front-side gate shield may overlap the channel region.

Abstract: A resistor may include a semiconductor layer having a source region, a drain region, and a channel region. The channel region may be between the source region and the drain region. The channel region may have a same polarity as the source region and the drain region. The resistor may further include a first inter-metal dielectric (IMD) layer on the channel region. The resistor may further include a front-side gate shield on the first IMD layer. The front-side gate shield may overlap the channel region.