Patents by Inventor Peter Graham Laws

Peter Graham Laws has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7038296
    Abstract: An electrical component structure (14) comprises a plurality of overlying substantially parallel layers (15, 16). Each layer (15, 16) provides a lattice (17, 20) comprising a first set of conductive tracks arranged substantially orthogonal to, and electrically connected with, a second set of conductive tracks. Conductive islands (18, 22) are located in windows of the lattices (17, 20), the conductive islands being electrically isolated from the tracks. The lattice (17, 20) of each layer (15, 16) is electrically connected to the conductive islands (22, 18) of the other adjacent layer (16, 15).
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: May 2, 2006
    Assignee: Zarlink Semiconductor Limited
    Inventor: Peter Graham Laws
  • Publication number: 20040222494
    Abstract: An electrical component structure (14) comprises a plurality of overlying substantially parallel layers (15, 16). Each layer (15, 16) provides a lattice (17, 20) comprising a first set of conductive tracks arranged substantially orthogonal to, and electrically connected with, a second set of conductive tracks. Conductive islands (18, 22) are located in windows of the lattices (17, 20), the conductive islands being electrically isolated from the tracks. The lattice (17, 20) of each layer (15, 16) is electrically connected to the conductive islands (22, 18) of the other adjacent layer (16, 15).
    Type: Application
    Filed: February 6, 2004
    Publication date: November 11, 2004
    Inventor: Peter Graham Laws
  • Patent number: 6781482
    Abstract: An integrated circuit having a substrate and an LC tank circuit comprises an inductor with parallel capacitors. The capacitors include triple plate integrated capacitors having a highest metal plate, a common middle plate and a lowest metal plate. The lowest plate is connected to a virtual ground node. A control circuit element connected to the middle plate allows the resonant frequency of the tank circuit to be controlled.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: August 24, 2004
    Assignee: Zarlink Semiconductor Limited
    Inventor: Peter Graham Laws
  • Patent number: 6664824
    Abstract: A frequency doubler circuit arrangement comprises a full wave rectifier circuit having an input and a first terminal, the first terminal being connected to a first supply terminal via a first current source, and the input forming an input of the frequency doubler circuit arrangement. A biased transistor circuit is also provided, having a first terminal connected to the first supply terminal via a second current source and being connected to the first terminal of the rectifier circuit. Output terminals of the rectifier circuit and the biased transistor circuit form differential output terminals of the frequency doubler circuit arrangement. The respective outputs of the rectifier circuit and the biased transistor circuit may be connected to a second supply terminal via either an active filter load or a passive filter load, such as an inductance-capacitance-resistance filter.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: December 16, 2003
    Assignee: Zarlink Semiconductor Limited
    Inventor: Peter Graham Laws
  • Patent number: 6642787
    Abstract: An amplifier circuit arrangement comprises first and second long-tailed pairs of transistors each including an inductor to provide a constant current source for their respective transistor pair. Each of the transistors of the pairs is provided with a bias current on its base electrode. A differential input signal is applied between the base electrode of one transistor, via a dc blocking capacitor and an input terminal, and the base electrode of another transistor, via a dc blocking capacitor and an another input terminal. The collector electrodes of two of the transistors are connected together and to an output terminal. The collector electrodes of the other two transistors similarly are connected together and to the other output terminal. A differential output signal is provided between the output terminals. This connection of the collectors of the transistors, which can be described as parallel connection, provides summation of the differential signals provided by the transistor pairs.
    Type: Grant
    Filed: March 16, 2000
    Date of Patent: November 4, 2003
    Assignee: Mitel Semiconductor Limited
    Inventors: Viatcheslav Igor Souetinov, Peter Graham Laws
  • Publication number: 20030142459
    Abstract: An integrated circuit having a substrate and an LC tank circuit comprises an inductor with parallel capacitors. The capacitors include triple plate integrated capacitors having a highest metal plate, a common middle plate and a lowest metal plate. The lowest plate is connected to a virtual ground node. A control circuit element connected to the middle plate allows the resonant frequency of the tank circuit to be controlled.
    Type: Application
    Filed: December 18, 2002
    Publication date: July 31, 2003
    Inventor: Peter Graham Laws
  • Publication number: 20030025537
    Abstract: A frequency doubler circuit arrangement comprises a full wave rectifier circuit having an input and a first terminal, the first terminal being connected to a first supply terminal via a first current source, and the input forming an input of the frequency doubler circuit arrangement. A biased transistor circuit is also provided, having a first terminal connected to the first supply terminal via a second current source and being connected to the first terminal of the rectifier circuit. Output terminals of the rectifier circuit and the biased transistor circuit form differential output terminals of the frequency doubler circuit arrangement. The respective outputs of the rectifier circuit and the biased transistor circuit may be connected to a second supply terminal via either an active filter load or a passive filter load, such as an inductance-capacitance-resistance filter.
    Type: Application
    Filed: July 24, 2002
    Publication date: February 6, 2003
    Applicant: Zarlink Semiconductor Limited
    Inventor: Peter Graham Laws
  • Patent number: 4104714
    Abstract: A DC to DC converter is provided which may form part of a battery powered gas ignition system, in which the converter comprises a chopper transistor, a transformer having current sensing circuits in the primary and secondary circuits thereof connected in the form of a relaxation oscillator and preferably a supply voltage sensing circuit for effecting a regulation of the battery current in order to obtain substantially maximum power from the battery throughout its useful life.
    Type: Grant
    Filed: January 14, 1977
    Date of Patent: August 1, 1978
    Assignee: Plessey Handel und Investments AG.
    Inventors: Richard Hanley Smith, Peter Graham Laws