Abstract: A liquid chromatograph includes a liquid chromatograph unit that has a pump sending an eluent to a detector and a control unit that controls the liquid to be sent by the pump based on a predetermined time table. The control unit stores an elution response of the liquid chromatograph unit which is obtained when a predetermined command value is input and another elution response which is obtained when the same command value is input to another liquid chromatograph. The time table is converted in the control unit based on the elution response and the other elution response to obtain respective elution profiles. In this manner, even when a measuring method related to another liquid chromatograph is used, it is possible to provide a liquid chromatograph capable of obtaining measurement results which are the same as those obtained when the measuring method is used in the other liquid chromatograph.

Abstract: A liquid chromatograph includes a liquid chromatograph unit that has a pump sending an eluent to a detector and a control unit that controls the liquid to be sent by the pump based on a predetermined time table. The control unit stores an elution response of the liquid chromatograph unit which is obtained when a predetermined command value is input and another elution response which is obtained when the same command value is input to another liquid chromatograph. The time table is converted in the control unit based on the elution response and the other elution response to obtain respective elution profiles. In this manner, even when a measuring method related to another liquid chromatograph is used, it is possible to provide a liquid chromatograph capable of obtaining measurement results which are the same as those obtained when the measuring method is used in the other liquid chromatograph.

Abstract: The digital interface unit (1) for control of a peripheral device, especially for controlling a magnetic valve for an injection device, includes a plurality of output registers (2 to 5), which store and output a set of control variables applied to the input sides of the respective output registers in response to a control signal (18, MST E). So that the control variables are output from the output registers exactly simultaneously even though they are received sequentially, at least one group of buffer registers (12 to 15, 24 to 27) is connected to the output registers (2 to 5). The buffer register or registers provides intermediate storage for the control variables prior to output from the interface unit.

Abstract: The external intelligent component (3) connected with a microprocessor system (2) is described for essentially automatic control of a control element (1) without burdening the microprocessor system operation. The control parameters for the control element (1) are written into a data memory (6) of the external component (3) from the microprocessor system (2) and are read out internally from the data memory (6) during normal operation of the external component (3). Control of the external component (3) is possible by the microprocessor system (2) without blocking the system bus (5,7) of the microprocessor system (2) using a control line from the microprocessor to a reset input (RESET) of a controller (13) of the external component (3).

Abstract: A clock signal loading device for a processor of a controller connected to a network and a clock signal loading method are provided. The device includes a first oscillator for generating a clock signal that can be loaded to the processor, a controllable clock signal changer for changing the clock signal generated by the first oscillator, and a control device connected to the network for generating a control signal for controlling the clock signal changer as a function of the communication signals transmitted over the network. This device and method allows the frequency of the clock signal needed by the processor to be tuned in a simple and flexible manner.

Abstract: A method for detecting erroneously programmed memory cells of a memory, in particular for detecting overprogrammed memory cells of a flash semiconductor memory. The memory includes a plurality of memory cells, which can be subdivided into a number of blocks that can be erased as a unit, which in turn can be divided into a group of subblocks that can be programmed as a unit. The erroneous programming of a memory cell of a subblock causes each subblock of a number of subblocks that can be represented by an erroneously programmed subgroup to have a similarly erroneously programmed memory cell.

Abstract: A method and circuit arrangements for detecting and evaluating dropouts or drop-ins on recording media, comprising reading and modifying the recorded digital signals, the size and type of fault being evaluated on the basis of fixed threshold levels. In the case of a dropout, for example, the fault is weighted by determining the differential of the envelope of the read signal. In the case of a drop-in, other noise signals are left out of consideration by nonlinear emphasis of the drop-in and appropriate choice of the threshold value. A circuit combination enables both dropouts and drop-ins to be detected and evaluated.

Abstract: A method and circuit arrangements for detecting and evaluating dropouts or drop-ins on recording media, comprising reading and modifying the recorded digital signals, the size and type of fault being evaluated on the basis of fixed threshold levels. In the case of a dropout, for example, the fault is weighted by determining the differential of the envelope of the read signal. In the case of a drop-in, other noise signals are left out of consideration by nonlinear emphasis of the drop-in and appropriate choice of the threshold value. A circuit combination enables both dropouts and drop-ins to be detected and evaluated.