Patents by Inventor Peter Guy Middleton
Peter Guy Middleton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11210576Abstract: According to the present techniques there is provided a data processing device, for applying to packaging, the device having a flexible substrate, the flexible substrate comprising: storage circuitry to store device data therein; processing circuitry to process the device data; and communication circuitry to communicate with a remote resource to transmit the device data thereto; sensor circuitry to generate sensed device data, and wherein the device is configured to store the sensed device data in the storage circuitry, process the sensed device data and/or transmit the sensed device data to a remote resource.Type: GrantFiled: July 18, 2018Date of Patent: December 28, 2021Assignee: ARM IP LimitedInventors: Geoffrey Wyman Blake, Hugo John Martin Vincent, Amyas Edward Wykes Phillips, Richard William Earnshaw, Peter Guy Middleton
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Publication number: 20210089853Abstract: According to the present techniques there is provided a data processing device, for applying to packaging, the device having a flexible substrate, the flexible substrate comprising: storage circuitry to store device data therein; processing circuitry to process the device data; and communication circuitry to communicate with a remote resource to transmit the device data thereto; sensor circuitry to generate sensed device data, and wherein the device is configured to store the sensed device data in the storage circuitry, process the sensed device data and/or transmit the sensed device data to a remote resource.Type: ApplicationFiled: July 18, 2018Publication date: March 25, 2021Inventors: Geoffrey Wyman Blake, Hugo John Martin Vincent, Amyas Edward Wykes Phillips, Richard William Earnshaw, Peter Guy Middleton
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Patent number: 7487367Abstract: The present invention provides a data processing apparatus and method for managing access to a memory within the data processing apparatus. The data processing apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, said plurality of modes including at least one non-secure mode being a mode in the non-secure domain and at least one secure mode being a mode in the secure domain, said processor being operable such that when executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode. Further, a memory is provided for storing data required by the processor, and consists of secure memory for storing secure data and non-secure memory for storing non-secure data.Type: GrantFiled: November 17, 2003Date of Patent: February 3, 2009Assignee: ARM LimitedInventors: Lionel Belnet, Nicolas Chaussade, Simon Charles Watt, Peter Guy Middleton
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Patent number: 7305534Abstract: The present invention provides a data processing apparatus and method for controlling access to a memory. The data processing apparatus has a secure domain and a non-secure domain, in the secure domain the data processing apparatus having access to secure data which is not accessible in the non-secure domain. The data processing apparatus comprises a device coupled to a memory via a device bus, and operable, when an item of data in the memory is required by the device, to issue onto the device bus a memory access request pertaining to either the secure domain or the non-secure domain. The memory is operable to store data required by the device, and contains secure memory for storing secure data and non-secure memory for storing non-secure data.Type: GrantFiled: November 17, 2003Date of Patent: December 4, 2007Assignee: Arm LimitedInventors: Simon Charles Watt, Lionel Belnet, David Hennah Mansell, Nicolas Chaussade, Peter Guy Middleton
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Patent number: 7213095Abstract: A data processing system is provided with a bus having separate write channels W and read channels R via which bus transactions are made. Bus transaction buffers 34 are provided within the bus structure to buffer write requests, particularly so as to alleviate problems associated with relatively slow bus slaves. The bus transaction buffers 34 are responsive to the memory addresses associated with write requests and read requests which pass through them to identify those to the same memory address, or memory addresses within a predetermined range, so as to either ensure a strict correct ordering of those transactions, read to follow write, or to satisfy a read following a write with a buffered write data value and then flushing the read request such that it does not reach its final destination.Type: GrantFiled: June 8, 2004Date of Patent: May 1, 2007Assignee: Arm LimitedInventors: Peter Guy Middleton, David John Gwilt, Ian Victor Devereux, Bruce James Mathewson, Antony John Harris, Richard Roy Grisenthwaite
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Patent number: 7171539Abstract: The present invention provides a data processing apparatus and method for controlling access to a memory in the data processing apparatus. The apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, said plurality of modes including at least one non-secure mode being a mode in the non-secure domain and at least one secure mode being a mode in the secure domain. The processor is operable such that when executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. A memory is operable to store data required by the processor and comprises secure memory for storing secure data and non-secure memory for storing non-secure data, the processor being operable to issue a memory access request when access to an item of data in the memory is required.Type: GrantFiled: November 17, 2003Date of Patent: January 30, 2007Assignee: ARM LimitedInventors: David Hennah Mansell, Michael Robert Nonweiler, Peter Guy Middleton
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Patent number: 6826670Abstract: The present invention relates to a technique for accessing memory units in a data processing apparatus. The data processing apparatus comprises of plurality of memory units for storing data values, a processor core for issuing an access request specifying an access to be made to the memory units in relation to a data value, and a memory controller for performing the access specified by the access request. Attribute generation logic is provided for determining from the access request one or more predetermined attributes verifying which of the memory units should be used when performing the access. However, the memory controller does not wait until such determination has been performed by the attribute generation logic before beginning the access.Type: GrantFiled: May 31, 2002Date of Patent: November 30, 2004Assignee: ARM LimitedInventors: Peter Guy Middleton, David Michael Bull, Gary Campbell
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Publication number: 20040177269Abstract: The present invention provides a data processing apparatus and method for managing access to a memory within the data processing apparatus. The data processing apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, said plurality of modes including at least one non-secure mode being a mode in the non-secure domain and at least one secure mode being a mode in the secure domain, said processor being operable such that when executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode. Further, a memory is provided for storing data required by the processor, and consists of secure memory for storing secure data and non-secure memory for storing non-secure data.Type: ApplicationFiled: November 17, 2003Publication date: September 9, 2004Applicant: ARM LIMITEDInventors: Lionel Belnet, Nicolas Chaussade, Simon Charles Watt, Peter Guy Middleton
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Publication number: 20040177261Abstract: The present invention provides a data processing apparatus and method for controlling access to a memory. The data processing apparatus has a secure domain and a non-secure domain, in the secure domain the data processing apparatus having access to secure data which is not accessible in the non-secure domain. The data processing apparatus comprises a device coupled to a memory via a device bus, and operable, when an item of data in the memory is required by the device, to issue onto the device bus a memory access request pertaining to either the secure domain or the non-secure domain. The memory is operable to store data required by the device, and contains secure memory for storing secure data and non-secure memory for storing non-secure data.Type: ApplicationFiled: November 17, 2003Publication date: September 9, 2004Inventors: Simon Charles Watt, Lionel Belnet, David Hennah Mansell, Nicolas Chaussade, Peter Guy Middleton
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Publication number: 20040143720Abstract: The present invention provides a data processing apparatus and method for controlling access to a memory in the data processing apparatus. The apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, said plurality of modes including at least one non-secure mode being a mode in the non-secure domain and at least one secure mode being a mode in the secure domain. The processor is operable such that when executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. A memory is operable to store data required by the processor and comprises secure memory for storing secure data and non-secure memory for storing non-secure data, the processor being operable to issue a memory access request when access to an item of data in the memory is required.Type: ApplicationFiled: November 17, 2003Publication date: July 22, 2004Applicant: ARM LIMITEDInventors: David Hennah Mansell, Michael Robert Nonweiler, Peter Guy Middleton
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Patent number: 6721861Abstract: A valid memory 2 is provided storing valid words 8 with bit positions indicating whether corresponding cache lines within a cache memory 7 store valid data. Flip-flop circuits 4 are provided to indicate whether or not the valid words 8 within the valid memory 2 are themselves valid. The number of valid words 8 corresponding to an individual flip-flop circuit 4 varies in dependence upon the size of the valid memory 2. Thus, for example, a single flip-flop circuit 4 may indicate whether one, two, four or eight valid words 8 from the valid memory 2 are storing valid data depending upon the particular size of the valid memory 2 employed.Type: GrantFiled: December 30, 2002Date of Patent: April 13, 2004Assignee: Arm LimitedInventors: Peter Guy Middleton, David Michael Bull
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Publication number: 20030188105Abstract: The present invention relates to the management of caches in a data processing apparatus. An ‘n’-way set-associative cache is disclosed, each way comprises a plurality of cache lines, each of said plurality of cache lines comprising a plurality of data words, each of said plurality of data words having associated therewith a unique address. The unique address includes an address portion. The ‘n’-way set-associative cache comprises a cache memory comprising ‘n’ memory units, each of the ‘n’ memory units having a plurality of entries, respective entries in each of the ‘n’ memory units being associated with the same address portion and being operable to store a data word having that same address portion within its unique address.Type: ApplicationFiled: August 26, 2002Publication date: October 2, 2003Applicant: ARM LimitedInventor: Peter Guy Middleton
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Publication number: 20030149841Abstract: The present invention relates to the management of caches in a data processing apparatus. An ‘n’-way set-associative cache is disclosed, each way comprises a plurality of cache lines, each of said plurality of cache lines comprising a plurality of data words, each of said plurality of data words having associated therewith a unique address. The unique address includes an address portion. The ‘n’-way set-associative cache comprises a cache memory comprising ‘n’ memory units, each of the ‘n’ memory units having a plurality of entries, respective entries in each of the ‘n’ memory units being associated with the same address portion and being operable to store a data word having that same address portion within its unique address.Type: ApplicationFiled: January 23, 2002Publication date: August 7, 2003Inventor: Peter Guy Middleton
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Publication number: 20030135701Abstract: A valid memory 2 is provided storing valid words 8 with bit positions indicating whether corresponding cache lines within a cache memory 7 store valid data. Flip-flop circuits 4 are provided to indicate whether or not the valid words 8 within the valid memory 2 are themselves valid. The number of valid words 8 corresponding to an individual flip-flop circuit 4 varies in dependence upon the size of the valid memory 2. Thus, for example, a single flip-flop circuit 4 may indicate whether one, two, four or eight valid words 8 from the valid memory 2 are storing valid data depending upon the particular size of the valid memory 2 employed.Type: ApplicationFiled: December 30, 2002Publication date: July 17, 2003Applicant: ARM LIMITEDInventors: Peter Guy Middleton, David Michael Bull
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Publication number: 20030126374Abstract: A valid memory 2 is provided storing valid words 8 with bit positions indicating whether corresponding cache lines within a cache memory 7 store valid data. Flip-flop circuits 4 are provided to indicate whether or not the valid words 8 within the valid memory 2 are themselves valid. The number of valid words 8 corresponding to an individual flip-flop circuit 4 varies in dependence upon the size of the valid memory 2. Thus, for example, a single flip-flop circuit 4 may indicate whether one, two, four or eight valid words 8 from the valid memory 2 are storing valid data depending upon the particular size of the valid memory 2 employed.Type: ApplicationFiled: December 28, 2001Publication date: July 3, 2003Inventors: David Michael Bull, Peter Guy Middleton
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Patent number: 6564301Abstract: The data processing apparatus comprises a cache having a plurality of cache lines for storing data values retrieved from a plurality of memory regions, when a data value from a first memory region is stored in the cache and is subsequently updated within the cache by a new data value, the new data value is not transferred to memory until that new data value is removed from the cache. A marker is associated with each cache line and is settable to indicate that the data values stored in the corresponding cache line are from said first memory region. A protection unit for controlling the transfer of data values between the cache and the memory, is arranged, when said data values are to be loaded from the memory into a cache line of the cache, to determine whether said data values are from said first memory region and to cause the marker to be set accordingly.Type: GrantFiled: July 6, 1999Date of Patent: May 13, 2003Assignee: ARM LimitedInventor: Peter Guy Middleton
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Patent number: 6532553Abstract: A data processing system is provided having a main processor 4 and a coprocessor 26. When in a debug mode, the main processor 4 and the coprocessor 26 are supplied with different instructions. The coprocessor 26 is supplied with a coprocessor debug data generation instruction (MCR) whilst the main processor 4 is supplied with a main processor data capture instruction (LDR). The coprocessor 26 responds to the MCR instruction by controlling debug data representing state of the data processing apparatus 2 to be placed upon a data bus 24 from where it is read by the main processor 4 under control of the LDR instruction.Type: GrantFiled: September 29, 1999Date of Patent: March 11, 2003Assignee: ARM LimitedInventors: David John Gwilt, Andrew Christopher Rose, Peter Guy Middleton, David Michael Bull
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Publication number: 20030037217Abstract: The present invention relates to a technique for accessing memory units in a data processing apparatus. The data processing apparatus comprises of plurality of memory units for storing data values, a processor core for issuing an access request specifying an access to be made to the memory units in relation to a data value, and a memory controller for performing the access specified by the access request. Attribute generation logic is provided for determining from the access request one or more predetermined attributes verifying which of the memory units should be used when performing the access. However, the memory controller does not wait until such determination has been performed by the attribute generation logic before beginning the access.Type: ApplicationFiled: May 31, 2002Publication date: February 20, 2003Inventors: Peter Guy Middleton, David Michael Bull, Gary Campbell
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Patent number: 6366978Abstract: A cache memory system 22 is described in which a content addressable memory 24 and a cache RAM memory 28 are provided. Each content addressable storage row has an associated hit line 18 and an access enable line 12. An index decoder 46 is provided for controlling cache replacement and cache maintenance operations. The hit line 18 is used for passing both hit signals to the cache RAM 28 and select signals generated by the index decoder 46. A gate 36 operating under control of a multiplexer controller 44 controls this dual-use of the hit line 18 in dependence upon a selected mode of operation. In some embodiments a fast block transfer may be performed by loading data from a first address A into the cache memory 22. A match for the TAG value of the first address A could then be performed and the corresponding hit signal asserted and latched within a latch 43.Type: GrantFiled: November 5, 1999Date of Patent: April 2, 2002Assignee: ARM LimitedInventors: Peter Guy Middleton, Michael Thomas Kilpatrick
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Patent number: 6353879Abstract: A data processing system 2 is provided with a processor core 4 that issues virtual addresses VA that are translated to mapped addresses MA by an address translation circuit 6 based upon a predicted address mapping. The mapped address MA is used for a memory access within a memory system 8. The mapped address MA starts to be used before a mapping validity circuit 6 has determined whether or not the predicted translation was valid. Accordingly, if the predicted address translation turns out to be invalid, then the memory access is aborted. The state of the processor core is preserved either by stretching the processor clock signal or by continuing the processor clock signal and waiting the processor 4. The memory system 8 then restarts the memory access with the correct translated address.Type: GrantFiled: February 19, 1999Date of Patent: March 5, 2002Assignee: Arm LimitedInventors: Peter Guy Middleton, David Michael Bull