Patents by Inventor Peter H. Decher

Peter H. Decher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and apparatus for flexible extension of electrical conductors beyond the edges of a substrate
    Patent number: 7572132
    Abstract: A flexible extension wafer translator includes a wafer translator portion, one or more flexible connectors extending outwardly therefrom, and a connector tab coupled to the distal end of each outwardly extending flexible connector. The flexible connectors may take any suitable form, including but not limited to, draped and pleated.
    Type: Grant
    Filed: July 17, 2007
    Date of Patent: August 11, 2009
    Assignee: Advanced Inquiry Systems, Inc.
    Inventors: Morgan T. Johnson, Peter H. Decher
  • Methods and apparatus for flexible extension of electrical conductors beyond the edges of a substrate
    Publication number: 20080248663
    Abstract: A flexible extension wafer translator includes a wafer translator portion, one or more flexible connectors extending outwardly therefrom, and a connector tab coupled to the distal end of each outwardly extending flexible connector. The flexible connectors may take any suitable form, including but not limited to, draped and pleated.
    Type: Application
    Filed: July 17, 2007
    Publication date: October 9, 2008
    Inventors: Morgan T. Johnson, Peter H. Decher
  • Tester architecture for testing semiconductor integrated circuits
    Patent number: 6956394
    Abstract: A modular tester architecture allows end-users to mix-and-match scan chain modules and clock driver modules. Modules are interconnected via a synchronization bus allowing the test modules to synchronize with each other so that each can perform its portion of the overall test at the proper time in relation to the testing performed by other modules. The modules can include a BIST driver module, a data acquisition module, networking interface modules, a controller module, a current measurement module, and a DC parametrics module, among others.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: October 18, 2005
    Assignee: Teseda Corporation
    Inventors: Ajit M. Limaye, Peter H. Decher, Horst R. Niehaus
  • Tester architecture for testing semiconductor integrated circuits
    Publication number: 20040232936
    Abstract: A modular tester architecture allows end-users to mix-and-match scan chain modules and clock driver modules. Modules are interconnected via a synchronization bus allowing the test modules to synchronize with each other so that each can perform its portion of the overall test at the proper time in relation to the testing performed by other modules. The modules can include a BIST driver module, a data acquisition module, networking interface modules, a controller module, a current measurement module, and a DC parametrics module, among others.
    Type: Application
    Filed: May 21, 2004
    Publication date: November 25, 2004
    Applicant: Teseda Corporation
    Inventors: Ajit M. Limaye, Peter H. Decher, Horst R. Niehaus