Abstract: A method of interconnecting a new node into a cluster of other nodes. The new node broadcasts a configuration (DP) packet describing itself to the other nodes of the cluster. The other nodes then respond by setting up communications information enabling the new node to directly communicate with a monitor process in the responding nodes and sending that information (DI packet) to the new node. The new node then sets up information enabling the responding nodes to communicate with a monitor process on the new node and sends that information (DC packet) to the responding nodes. The responding nodes then acknowledge the information (DA packet) and the new node is then interconnected with the responding nodes. The DP and DI packets are sent via a permissive interrupt mechanism, received by each processor unit making up a node and forwarded to the monitor process of the node.

Abstract: A multiprocessor (MP) computer sytem which allows target CPU(s) to continue processing instructions while other target CPU(s) are processing instructions of emulation code to reach their end of a Domain Unit of Operation before synchronization. A two-level MP sync is used since the target CPUs must be in between units of operation when the updates occur since a unit of operation can be one instruction or it can be many instructions that together emulate one instruction. Two level MP sync allows CPUs that are going to be serialized to continue to process single instructions (no emulation code) while other target CPUs are in emulation mode.

Abstract: An access control apparatus in a computer system for controlling access to an ALB. A host ALBID register and a guest ALBID register is provided for storing a host and a guest ALB identifier (ALBID) and a host and a guest ALBID validity indicator. Control State Software generates and stores the host and guest ALBIDs in the host and guest ALBID registers and marks valid the host and guest ALBID validity indicator whenever a host or guest mode is initiated or a logical purge is requested by a logical processor and for storing the host or guest ALBID stored in the host and guest ALBID registers when an ALB entry is made in the ALB by a logical processor.

Abstract: In a computer system including an interrupt processor for interrupting a program being processed by the computer system, a sub-system for processing interrupt requests to the interrupt processor. The sub-system comprises hardware circuit for generating hardware interrupt requests and control circuit for implementing control software where the control software causing software interrupt requests to be generated by said control circuit. An interrupt register stores and identifies both the hardware and software interrupt requests. A selection circuit selects and sends one of said stored interrupt request stored in the interrupt register to the interrupt processor for processing. The control circuit, under control of the control software, generates an end software interrupt requests for removing software interrupt request stored in the interrupt register such that software interrupt in the computer system can be generated and terminated under the control of the control software.

Abstract: A computer system having a chief system control program running in a real machine as a host where the host controls standard system control programs (SCP's) and controls virtual machines (Domains) called guests. Guests operate with interpretive execution as second-level guests. Control is transferred from a second-level guest to the guest SCP or to the chief SCP with only one control interception. Control is transferred directly between the second-level guest and the Chief SCP bypassing the first-level guest.