Abstract: A multiplying circuit comprising a pair of transistors including first and second transistors arranged in a long-tailed pair configuration having a collector output and interconnected emitter electrodes coupled to a first current source. A bias voltage adjusting circuit applies equal base bias voltages to the base electrodes of the pair of transistors. The base electrodes are connected to a signal input to provide control of the amplitude of the output signal. The multiplying circuit further comprises a controlled current distribution circuit including a shunting transistor whose collector-emitter path is DC connected in parallel to the pair of transistors. A control circuit supplies a control voltage between the base electrode of the shunting transistor and the base electrodes of the pair of transistors.