Patents by Inventor Peter H. Spalding

Peter H. Spalding has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6686652
    Abstract: An assembly and method suitable for use in packaging integrated circuits including a support substrate for supporting an integrated circuit die embedded in a molded encapsulating cap. The substrate includes a conductive die attach pad adapted to be molded into the encapsulating cap. The pad includes an interior facing support surface and a spaced-apart exterior facing exposed surface defined by a peripheral edge. The support surface is adapted to support the embedded die, while the exposed surface is to be exposed from the encapsulating cap. The attach pad further includes a locking ledge portion extending outward peripherally beyond at least a portion of the exposed surface peripheral edge. This ledge is adapted to be subtended in the encapsulating cap in a manner substantially preventing a pull-out of the attach pad in a direction away from the encapsulating cap.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: February 3, 2004
    Assignee: National Semiconductor
    Inventors: Jaime Bayan, Peter H. Spalding, Harry Cheng-Hong Kam, Ah Lek Hu, Sharon Mei Wan Ko, Santhiran Nadarajah, Aik Seng Kang, Yin Yen Bong
  • Patent number: 5986332
    Abstract: A lead frame includes a die attach pad having a certain area with a portion of the area being adapted to receive and support an integrated circuit die. The lead frame also includes a plurality of leads for electrically connecting the integrated circuit die to other electrical elements external to the package. At least one of the leads is configured to have a portion of the lead overhang, but be spaced slightly apart from, the area of the die attach pad. The overhanging portions of the leads are positioned in close proximity to the die attach pad in order to improve the thermal transfer from the die attach pad to the leads during the operation of the integrated circuit package. A method of forming the lead frame includes the step of folding at least a portion of the lead frame which includes at least one of the leads such that the at least one lead is positioned with a portion of that lead overhanging, but being spaced slightly apart from, the die attach pad.
    Type: Grant
    Filed: August 12, 1998
    Date of Patent: November 16, 1999
    Assignee: National Semiconductor Corporation
    Inventors: Chin Seng Chu, Peter H. Spalding
  • Patent number: 5629563
    Abstract: A multi-chip packaging arrangement that contemplates stacking discrete components over film based components is disclosed. The multi-chip package includes a substrate having one or more film based components formed thereon. A discrete component is mounted on the substrate over the film based component such that it is electrically isolated from the film based component. One or more die components are also mounted on the substrate and a plurality of leads are provided for electrically connecting the multi-chip package to external circuitry. Wiring traces formed on the substrate are provided to electrically connect various ones of the components and the leads. A packaging material is provided to encapsulate the components and the wiring traces and leaves a portion of the leads exposed to facilitate electrically connecting the multi-chip package to external circuitry. Methods of making such multi-chip packages are also disclosed.
    Type: Grant
    Filed: November 7, 1995
    Date of Patent: May 13, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Hem P. Takiar, Uli H. Hegel, Peter H. Spalding, James L. Crozier, Michelle M. Hou-Chang, Martin A. Delateur