Abstract: The disclosed embodiments relate to a method for the production of a layer arrangement, a layer arrangement and a memory arrangement. According to one aspect at least one respectively laterally defined first layer sequence is embodied on a first surface area of a substrate and at least one respectively laterally defined second layer sequence is embodied on a second surface area of the substrate in order to produce a layer arrangement. A first side wall having a first thickness is respectively produced from a first electrically insulating material on at least one partial area of the side walls of the first and second layer sequences. A second side wall layer having a second thickness is respectively produced from a second electrically insulating material on at least one partial area of the first side wall layers and the second side wall layers are removed from the first layer sequences.

Abstract: A programmable read-only memory cell and method of operating the programmable read-only memory cell. In one embodiment, the programmable read-only memory cell comprises a floating gate arranged in a trench, an epitaxial channel layer formed on the floating gate, the channel layer connecting a source electrode to a drain electrode, and a selection gate arranged above the channel line.

Abstract: The disclosed embodiments relate to a method for the production of a layer arrangement, a layer arrangement and a memory arrangement. According to one aspect at least one respectively laterally defined first layer sequence is embodied on a first surface area of a substrate and at least one respectively laterally defined second layer sequence is embodied on a second surface area of the substrate in order to produce a layer arrangement. A first side wall having a first thickness is respectively produced from a first electrically insulating material on at least one partial area of the side walls of the first and second layer sequences. A second side wall layer having a second thickness is respectively produced from a second electrically insulating material on at least one partial area of the first side wall layers and the second side wall layers are removed from the first layer sequences.

Abstract: A programmable read-only memory cell and method of operating the programmable read-only memory cell. In one embodiment, the programmable read-only memory cell comprises a floating gate arranged in a trench, an epitaxial channel layer formed on the floating gate, the channel layer connecting a source electrode to a drain electrode, and a selection gate arranged above the channel line.

Abstract: A vertical transistor (100) has a source region (103), a drain region (109), a gate region (108), and a channel region (104) between the source region (103) and the drain region (109), which are arranged in a vertical direction in a semiconductor substrate (101), the gate region (104) having an electrical insulation from the source region (103), from the drain region (109) and from the channel region (104) and being arranged around the channel region (104) in such a way that the gate region (108) and the channel region (104) form a coaxial structure.

Abstract: A vertical transistor (100) has a source region (103), a drain region (109), a gate region (108), and a channel region (104) between the source region (103) and the drain region (109), which are arranged in a vertical direction in a semiconductor substrate (101), the gate region (104) having an electrical insulation from the source region (103), from the drain region (109) and from the channel region (104) and being arranged around the channel region (104) in such a way that the gate region (108) and the channel region (104) form a coaxial structure.