Abstract: A data memory for storing elements, which data memory stores the data of the elements and at least a chained list which contains, for each stored element, at least its element address, its element number and a pointer to the address of the stored element having the next-higher element number. There are also provided an element status table, in which the element numbers of the elements present in the data memory are taken up, and also an address reference table which contains the element addresses for all element numbers.

Abstract: In the case of a master node (1) for a LIN network (Local Interconnect Network) (9), hardware circuits (2, 3, 4, 5) are rovided in the master node (1), which hardware circuits are provided to carry out the LIN protocol and take over the behavior of the master during data transmission or data reception without additional processor or software support.

Abstract: A data memory for storing elements, which data memory stores the data of the elements and at least a chained list which contains, for each stored element, at least its element address, its element number and a pointer to the address of the stored element having the next-higher element number. There are also provided an element status table, in which the element numbers of the elements present in the data memory are taken up, and also an address reference table which contains the element addresses for all element numbers.

Abstract: A method for use in a CAN device (e.g., a CAN microcontroller) that includes a processor core and hardware external to the processor core (e.g., a DMA engine) that writes message data into a designated message buffer for ensuring integrity of the message data stored in the designated message buffer. The method includes providing a three-state semaphore to indicate a current access status of the designated message buffer, the three-state semaphore having a first state indicative of the hardware external to the processor core starting to write new message data into the designated message buffer, a second state indicative of the hardware external to the processor core having finished writing the new message data into the designated message buffer, and, a third state indicative of the processor core starting to read message data from the designated message buffer. The processor core determines whether the designated message buffer is ready to be accessed based on the current state of the semaphore.

Abstract: An acceptance filter (1) according to the invention for filtering identifiers in messages which may be exchanged between users (2, 3, 4) over a data bus takes the form solely of a hardware circuit and is provided jointly for the allocated users (2, 3, 4). An identifier received by an allocated user (2, 3, 4) is compared locally with stored identifiers and examined to see whether the message to which the received identifier belongs is relevant to the allocated user (2, 3, 4) that received it and where appropriate a corresponding acceptance signal is sent to this allocated user (2, 3, 4).