Abstract: In an assembly (2) for an airplane (4) with a line (12) and switching elements (14a,b) to connect the line (12) in a first operating mode (B1) to digital transceivers (16a,b) and in a second operating mode (B2) to an analog signal source/sink (18a,b) for the audio signal (A), the line (12) is operated in the first operating mode (B1) as a digital data bus for data (D) and in the second operating mode (B2) as an analog signal line for transmitting an analog audio signal (A) from the signal source (18a) to the signal sink (18b). In a corresponding method, the line (12) is operated in a first operating mode (B1) as a digital data bus for transmitting data (D) and the line (12) is switched to the second operating mode (B2) for transmitting the audio signal (A), and the audio signal (A) is transmitted from the signal source (18a) via the line (12) to the signal sink (18b).

Abstract: In an assembly (2) for an airplane (4) with a line (12) and switching elements (14a,b) to connect the line (12) in a first operating mode (B1) to digital transceivers (16a,b) and in a second operating mode (B2) to an analog signal source/sink (18a,b) for the audio signal (A), the line (12) is operated in the first operating mode (B1) as a digital data bus for data (D) and in the second operating mode (B2) as an analog signal line for transmitting an analog audio signal (A) from the signal source (18a) to the signal sink (18b). In a corresponding method, the line (12) is operated in a first operating mode (B1) as a digital data bus for transmitting data (D) and the line (12) is switched to the second operating mode (B2) for transmitting the audio signal (A), and the audio signal (A) is transmitted from the signal source (18a) via the line (12) to the signal sink (18b).

Abstract: A bus architecture has a central processing unit, a data line and bus users. The central processing unit and the bus users are connected to the data line via a bus interface. The data line is constructed as a ring and the central processing unit has two transceiver units which can be switched between transmit and receive modes. The central processing unit provides a clocked emission of data intended for the bus users. The bus users are successively connected to the data line, and each contains a monitoring unit, which is connected to the associated bus interface and is configured for activating a transmit activity of the bus interface only after receiving a synchronization message, and otherwise blocks this activity. In a method for exchanging data with such a bus architecture, a high fault tolerance, particularly when the data line is cut through, and error locating capability are achieved.

Abstract: A bus architecture has a central processing unit, a data line and bus users. The central processing unit and the bus users are connected to the data line via a bus interface. The data line is constructed as a ring and the central processing unit has two transceiver units which can be switched between transmit and receive modes. The central processing unit provides a clocked emission of data intended for the bus users. The bus users are successively connected to the data line, and each contains a monitoring unit, which is connected to the associated bus interface and is configured for activating a transmit activity of the bus interface only after receiving a synchronization message, and otherwise blocks this activity. In a method for exchanging data with such a bus architecture, a high fault tolerance, particularly when the data line is cut through, and error locating capability are achieved.