Patents by Inventor Peter Hofstee
Peter Hofstee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6717882Abstract: An improved cell circuit for data readout for use in a multiport memory is provided. The multiport memory stores write data signals. The cell circuit includes a plurality of multiplexers each coupled to a discharge device. Each of the multiplexers receives a subset of the write data signals and a plurality of read wordline signals and selects an output enable signal among the subset of the write data signals based on the read wordline signals. Each of the discharge devices are coupled to one of the multiplexers for receiving the output enable signal to generate a drive signal for driving one or more bitlines of the multiport memory.Type: GrantFiled: October 17, 2002Date of Patent: April 6, 2004Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Harm Peter Hofstee, Shoji Onishi, Osamu Takahashi
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Publication number: 20040051713Abstract: A system, method, and computer program product are provided for generating display data. The data processing system loads coefficient values corresponding to a behavior of a selected function in pre-defined ranges of input data. The data processing system then determines, responsive to items of input data, the range of input data in which the selected function is to be estimated. The data processing system then selects, through the use of a vector permute function, the coefficient values, and evaluates an index function at the each of the items of input data. It then estimates the value of the selected function through parallel mathematical operations on the items of input data, the selected coefficient values, and the values of the index function, and, responsive to the one or more values of the selected function, generates display data.Type: ApplicationFiled: September 12, 2002Publication date: March 18, 2004Applicant: International Business Machines CorporationInventors: Gordon Clyde Fossum, Harm Peter Hofstee, Barry L. Minor, Mark Richard Nutter
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Patent number: 6708267Abstract: A pipelined processor and method are disclosed for speculatively determining dependencies. The processor processes a plurality of instructions in order. A speculative detection circuit which takes multiple clock cycles to operate determines whether a dependency exists. The speculative detection circuit inserts a single-cycle pipeline stall only in response to a determination that a speculative dependency exists.Type: GrantFiled: February 4, 2000Date of Patent: March 16, 2004Assignee: International Business Machines CorporationInventors: Brian King Flacks, Harm Peter Hofstee, Osamu Takahashi
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Patent number: 6675182Abstract: A method and apparatus performing rotate operations using cascaded multiplexers provides a scalable rotator circuit having a sub-field rotate capability that requires no additional interconnects at the sub-field endpoints. The rotator performs bit field swap operations at each stage of a series of cascaded multiplexers. The bit field size increases monotonically from a single bit to half of the rotator operand size. The control logic selects swap operations for each individual bit field at each stage, in order to arrange a desired rotated output vector.Type: GrantFiled: August 25, 2000Date of Patent: January 6, 2004Assignee: International Business Machines CorporationInventors: H. Peter Hofstee, Hung C. Ngo, Kevin J. Nowka, Jun Sawada
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Patent number: 6629235Abstract: A condition code register architecture for supporting multiple execution units is disclosed. A master execution unit is coupled a master condition code register such that condition codes generated by the master execution unit are stored in the master condition code register. A non-master execution unit is coupled to a shadow condition code register such that condition codes generated by the non-master execution unit are stored in the shadow condition code register. A tag unit coupled to the master execution unit and the non-master execution unit such that an entry within the master condition code register can be read only when a corresponding entry within the tag unit is referenced to the master execution unit or the master condition code register.Type: GrantFiled: May 5, 2000Date of Patent: September 30, 2003Assignee: International Business Machines CorporationInventors: Brian King Flachs, Harm Peter Hofstee, Kevin John Nowka
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Patent number: 6600959Abstract: A method and apparatus for using dynamic programmable logic arrays in microprocessor control logic provide decreased power and increased clock frequencies for data processing systems, by using programmable logic arrays exclusively for the control logic. The method and apparatus further simplify the design of the control logic and closure of timing within the microprocessor, by providing overlap of control logic evaluations and data transfers within the microprocessor.Type: GrantFiled: February 4, 2000Date of Patent: July 29, 2003Assignee: International Business Machines CorporationInventors: Paula Kristine Coulman, Sang Hoo Dhong, Brian King Flachs, Harm Peter Hofstee, Jaehong Park, Stephen Douglas Posluszny, Joel Abraham Silberman, Osamu Takahashi
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Patent number: 6598153Abstract: A processor that promotes accelerated resolution of conditional branch instructions includes an instruction sequencer that fetches a plurality of instructions and a detector that detects, among the plurality of fetched instructions, a condition-setting instruction and a conditional branch instruction that depends upon the condition-setting instruction. The processor further includes a decoder that decodes the conditional branch instruction to produce a decoded condition type and an execution unit. In response to the detection of the condition-setting instruction and the conditional branch instruction, the execution unit resolves the conditional branch instruction by evaluating the condition-setting instruction and the decoded condition type in a single operation. Because the condition code bits are not computed or stored as an intermediate result as in prior art processors, branch resolution is accelerated.Type: GrantFiled: December 10, 1999Date of Patent: July 22, 2003Assignee: International Business Machines CorporationInventors: Brian King Flachs, Harm Peter Hofstee, Kevin John Nowka
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Patent number: 6587941Abstract: A pipelined processor and method are disclosed including an improved history file unit. The pipelined processor processes a plurality of instructions in order. A register file is included which includes a different read port coupled to each register field in an instruction buffer for reading data from the register file. A history file unit is included and is coupled to each of the read ports of the register file for receiving a copy of all data read from the register file.Type: GrantFiled: February 4, 2000Date of Patent: July 1, 2003Assignee: International Business Machines CorporationInventors: Brian King Flacks, Harm Peter Hofstee, Osamu Takahashi
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Publication number: 20030115500Abstract: A system including a central processor and a plurality of attached processors all on a single die are disclosed Each of the attached processors is preferably functionally equivalent to each of the other attached processors. The system further includes at least one redundant processor that is connectable to the central processor. The redundant processor may be substantially equivalent to each of the attached processors. Upon detecting a failure in one of the attached processors, the system is configured to disable the non-functional processor and enable the redundant processor. The attached processors may be connected to a memory interface unit via a parallel bus or a pipelined bus in which each attached processor is connected to a stage of the pipelined bus. The attached processors may each include a load store unit and logic suitable for performing a mathematical function.Type: ApplicationFiled: December 14, 2000Publication date: June 19, 2003Applicant: International Business Machines CorporationInventors: Chekib Akrout, Harm Peter Hofstee, James Allan Kahle
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Publication number: 20030101207Abstract: A method and apparatus for adding and multiplying floating-point operands such that a fixed-size mantissa result is produced. In accordance with the present addition method, the mantissa of a first floating-point operand is shifted in accordance with relative operand exponent information. Next, the first operand mantissa is added to the second operand mantissa. The addition step includes replacing a least significant non-overlapped portion of the first operand mantissa with a randomly-generated carry-in bit. In accordance with the multiplication method, a partial product array is generated from a pair of floating-point operand mantissas. Next, prior to compressing the partial product array into a compressed mantissa result, a lower-order bit portion of the partial product array is replaced with a randomly generated carry-in value.Type: ApplicationFiled: November 29, 2001Publication date: May 29, 2003Applicant: International Business Machines CorporationInventors: Sang Hoo Dhong, Harm Peter Hofstee, Kevin Nowka, Stephen Douglas Posluszny, Joel Abraham Silberman
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Publication number: 20030056064Abstract: There is provided a method for aligning and inserting data elements into a memory based upon an instruction sequence consisting of one or more alignment instructions and a single store instruction. Given a data item that includes a data element to be stored, the method includes the step of aligning the data element in another memory with respect to a predetermined position in the memory, in response to the one or more alignment instructions. A mask is dynamically generated to enable writing of memory bit lines that correspond to the aligned data element. The memory bit lines are written to the memory under a control of the mask. The generating and writing steps are performed in response to the single store instruction.Type: ApplicationFiled: August 28, 2001Publication date: March 20, 2003Inventors: Michael K. Gschwind, Martin E. Hopkins, H. Peter Hofstee
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Publication number: 20030037221Abstract: An improved processor implementation is described in which scalar and vector processing components are merged to reduce complexity. In particular, the implementation includes a scalar-vector register file for storing scalar and vector instructions, as well as a parallel vector unit comprising functional units that can process vector or scalar instructions as required. A further aspect of the invention provides the ability to disable unused functional units in the parallel vector unit, such as during a scalar operation, to achieve significant power savings.Type: ApplicationFiled: August 14, 2001Publication date: February 20, 2003Applicant: International Business Machines CorporationInventors: Michael Karl Gschwind, Harm Peter Hofstee, Martin Edward Hopkins
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Patent number: 6518793Abstract: The present invention relates to improvements concerning logic and timing verification as the testability of a hardware circuit comprising embeddings of dynamic logic circuits in a static environment. The clocked macros comprising the dynamic logic circuit are bounded at both input and output by latches, keeping input and output signals to the clocked macro static. The static input signals are processed with wave formatting means in order to generate a wave form usable for an evaluation by the dynamic logic circuit, and the dynamic logic output signal is converted back to a static signal by a set/reset latch such that it can be latched by the clock signal of the static embedding circuit. Thus, the analysis methods for timing and logic simulation during chip design can be the same as those used for static logic and, in particular, the LSSD testing methods can be used.Type: GrantFiled: March 22, 2001Date of Patent: February 11, 2003Assignee: International Business Machines CorporationInventors: Jens Leenstra, Hans-Werner Tast, Dieter Wendel, Peter Hofstee
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Publication number: 20030023948Abstract: The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block (16) and then performing logic synthesis (17) for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design (29) which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit (29) is produced, the circuit design method includes eliminating unnecessary devices (46) from the intermediate circuit (29) to produce a final logic circuit, and then sizing the devices (48) in the final circuit to complete the design.Type: ApplicationFiled: July 26, 2001Publication date: January 30, 2003Inventors: Sang Hoo Dhong, Harm Peter Hofstee, Stephen Douglas Posluszny, Joel Abraham Silberman, Osamu Takahashi, Dieter F. Wendel
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Publication number: 20030023889Abstract: A transitioning of power dissipation in a processing device (11) is coordinated with the operation of a cooling system (16, 17, 18) for the processing device. A power transitioning arrangement (15) transitions power dissipation in the processing device (11) between a high power level and a relatively lower low power level. In conjunction with a transitioning of the processing device power level, the cooling system (16, 17, 18) is placed in either a high or low thermal impedance state to reduce the rate at which the temperature of the data processing device (11) and related elements change in response to the change in power dissipated by the processing device. Transitioning the power dissipation in the processing device (11) may be accomplished by gradually varying the clock rate for the device, by changing the clock rate to various processing elements in the device at different times, and/or by changing the instruction issue rate in the device.Type: ApplicationFiled: July 26, 2001Publication date: January 30, 2003Inventors: Harm Peter Hofstee, Gordon J. Robbins
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Patent number: 6507115Abstract: A multi-chip module is disclosed in which a first die connects to a second set of die via a set of C4 connections within a single package. Low resistivity signal posts are provided within the lateral separation between adjacent die in the second set of die. These signal posts are connectable to externally supplied power signals. The power signals provided to the signals posts are routed to circuits within the second set of die over relatively short metallization interconnects. The signal posts may be connected to thermally conductive via elements and the package may include heat spreaders on upper and lower package surfaces. The first die may comprise a DRAM while the second set of die comprise portions of a general purpose microprocessor. The power signals provided to the second set of die may be connected to a capacitor terminal in the first die to provide power signal decoupling.Type: GrantFiled: December 14, 2000Date of Patent: January 14, 2003Assignee: International Business Machines CorporationInventors: Harm Peter Hofstee, Robert Kevin Montoye, Edmund Juris Sprogis
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Publication number: 20030005237Abstract: A processor-cache operational scheme and topology within a multi-processor data processing system having a shared lower level cache (or memory) by which the number of coherency busses is reduced and more efficient snoop resolution and coherency operations with the processor caches are provided. A copy of the internal (L1) cache directory is provided within the lower level (L2) cache or memory. The snoop operations and coherency maintenance operations of the L1 directory are completed by comparing the snoop addresses with the address tags of the copy of the L1 directory in the L2 cache. Updates to the coherency states of the copy of the L1 directory are mirrored in the L1 directory and L1 cache. This eliminates the need for the individual coherency buses of each processor that is coupled to the L2 cache and speeds up coherency operations because the snoops do not have to be transmitted to the L1 caches.Type: ApplicationFiled: June 29, 2001Publication date: January 2, 2003Applicant: International Business Machines Corp.Inventors: Sang Hoo Dhong, Harm Peter Hofstee, Charles Ray Johns, John Samuel Liberty, Thuong Quang Truong
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Patent number: 6502224Abstract: A method and apparatus for synthesizing logic circuits with synchronized outputs is disclosed. A logic designer selects a fixed number of levels in which to synthesize the circuit, each level implementing a plurality of different logic function all having the same propagation delay. Circuit outputs are synchronized by ensuring that each logic function is synthesized by connecting logic functions from level to level such that each signal path passes through each level once and only once.Type: GrantFiled: April 12, 2001Date of Patent: December 31, 2002Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Harm Peter Hofstee, Stephen Douglas Posluszny, Joel Abraham Silberman, Osamu Takahashi, Dieter F. Wendel
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Publication number: 20020163881Abstract: A communications bus (300) includes a number of alternate transmission paths (311, 312) between a given source node (301) and respective destination node (305) on a common substrate. The source node (301) receives a signal from a first circuit (309) serviced by the bus (300) while the respective destination node (305) transfers that signal to a second circuit (310) serviced by the bus. The communications bus (300) includes two switching arrangements for switching between the alternate transmission paths (311, 312). A source switching arrangement (318) is interposed between the source node (301) and the respective alternate transmission path (311, 312). This source switching arrangement (318) selectively connects the respective source node (301) to a selected one of the alternate transmission paths (311, 312) and disconnects the source node (301) from each other alternate transmission path.Type: ApplicationFiled: May 3, 2001Publication date: November 7, 2002Inventors: Sang Hoo Dhong, Harm Peter Hofstee
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Publication number: 20020156999Abstract: A mixed-mode multithreading processor is provided. In one embodiment, the multi-mode multithreading processor includes a multithreaded register file with a plurality of registers, a thread control unit, and a plurality of hold latches. Each of the hold latches and registers stores data representing a first instruction thread and a second instruction thread. The thread control unit provides thread control signals to each of the hold latches and registers selecting a thread using the data. The thread control unit provides control signals for interleaving multithreading except when a long latency operation is detected in one of the threads. During a predetermined period corresponding approximately to the duration of the long latency operation, the thread control unit places the processor in a mode in which only instructions corresponding to the other thread are read out of the hold latches and registers. Once the predetermined period of time has expired, the processor returns to interleaving multithreading.Type: ApplicationFiled: April 19, 2001Publication date: October 24, 2002Applicant: International Business Machines CorporationInventors: Richard James Eickemeyer, Harm Peter Hofstee, Charles Roberts Moore, Ravi Nair