Abstract: System and method for running a software application, such as a video game for many users. In one embodiment a multi-user computer-controlled video gaming system comprising: at least one display device for displaying video game motion pictures to the plurality of users; a plurality of user input devices, at least one for each user, providing user input data to the computer-controlled video gaming system; a processing unit receiving and processing the user input data from the plurality of input devices to generate control input data for a conjointly control of at least one game mechanic of the performed game; at least one computing device executing a game software application for performing said game, the at least one computing device being controlled by said control input data for providing output to the display device to display the video game motion pictures dependent on said at least one conjointly controlled game mechanic.

Abstract: System and method for running a software application, such as a video game for many users. In one embodiment a multi-user computer-controlled video gaming system comprising: at least one display device for displaying video game motion pictures to the plurality of users; a plurality of user input devices, at least one for each user, providing user input data to the computer-controlled video gaming system; a processing unit receiving and processing the user input data from the plurality of input devices to generate control input data for a conjointly control of at least one game mechanic of the performed game; at least one computing device executing a game software application for performing said game, the at least one computing device being controlled by said control input data for providing output to the display device to display the video game motion pictures dependent on said at least one conjointly controlled game mechanic.

Abstract: Three-value modulo-2-adders consist of four circuit components (SC1, SC2, SC3, SC4) and an analysis circuit (AW). The first circuit component (SC1) generates an intermediate signal corresponding to the first binary value ("1") when two of the input signals (A, B, C) each assume the other binary value ("0"). The second circuit component (SC2) generates an intermediate signal (ZS2) corresponding to the other binary value when two input signals each assume the first binary value. The intermediate value emitted from the output of the third circuit component (SC3) is binary "0" when all three input signals assume the binary value "1". The fourth circuit component (SC4) emits the binary value "1" when all the input signals have the binary value "0".