Abstract: A class-D amplifier includes an output driver stage and a current sensing circuit connected. The current sensing circuit includes: an operational amplifier having a positive input terminal and a negative input terminal; a positive input replica transistor, where a source of the positive input replica transistor is connected to the positive input terminal, a drain and a gate of the positive input replica transistor is connected to the drain and the gate of a first n-type output transistor, respectively; and a negative input replica transistor, where a source of the negative input replica transistor is connected to the negative input terminal, a drain and a gate of the negative input replica transistor is connected to the drain and the gate of the second n-type output transistor, respectively.

Abstract: A class-D amplifier includes an output driver stage and a current sensing circuit connected. The current sensing circuit includes: an operational amplifier having a positive input terminal and a negative input terminal; a positive input replica transistor, where a source of the positive input replica transistor is connected to the positive input terminal, a drain and a gate of the positive input replica transistor is connected to the drain and the gate of a first n-type output transistor, respectively; and a negative input replica transistor, where a source of the negative input replica transistor is connected to the negative input terminal, a drain and a gate of the negative input replica transistor is connected to the drain and the gate of the second n-type output transistor, respectively.

Abstract: An audio driver circuit includes a modulator circuit configured to receive an audio input signal and produce a first modulated digital pulse signal. The first modulated digital pulse signal has a magnitude that switches between a supply power voltage and a supply ground voltage. The audio driver circuit also includes a switched driver circuit coupled to the modulator circuit to receive the first modulated digital pulse signal and configured to provide a second modulated digital pulse signal for driving an MOS (metal oxide semiconductor) output transistor. The second modulated digital pulse signal has a same timing pattern as the first modulated digital pulse signal and has a magnitude that tracks linearly with the magnitude of the audio input signal.

Abstract: An audio driver circuit includes a modulator circuit configured to receive an audio input signal and produce a first modulated digital pulse signal. The first modulated digital pulse signal has a magnitude that switches between a supply power voltage and a supply ground voltage. The audio driver circuit also includes a switched driver circuit coupled to the modulator circuit to receive the first modulated digital pulse signal and configured to provide a second modulated digital pulse signal for driving an MOS (metal oxide semiconductor) output transistor. The second modulated digital pulse signal has a same timing pattern as the first modulated digital pulse signal and has a magnitude that tracks linearly with the magnitude of the audio input signal.

Abstract: A PDM (pulse density modulation) signal energy detection circuit includes a digital-to-analog converter circuit for receiving a PDM digital input signal and producing an analog output signal based on the PDM digital input signal. The PDM signal energy detection circuit also includes a comparator circuit for receiving the analog output signal from the digital-to-analog converter circuit and producing a pulsed signal when a magnitude of the analog output signal exceeds a pre-set threshold. The PDM signal energy detection circuit also has a counter circuit for receiving the pulsed signal from the comparator circuit and producing an energy detection signal when a number of consecutive pulsed signals exceed a pre-set count.

Abstract: An acoustic energy detection circuit can include a microphone interface circuit configured for coupling to a microphone. The microphone interface circuit is configured to intermittently activate the microphone to detect acoustic energy and convert the acoustic energy to an electrical signal. The acoustic energy detection circuit also includes a comparator circuit for receiving the electrical signal and comparing the electrical signal with a threshold signal. The comparator circuit is configured to output an output signal to indicate detection of acoustic energy.

Abstract: An integrated oscillator circuit has a plurality oscillator stages including a first oscillator stage, an odd number of intermediate oscillator stages, and a last oscillator stage arranged in series. Each of the oscillator stages has a reverse-biased diode device and a transistor coupled in series between a power supply and a ground. Each diode device has an anode and a cathode, and each transistor has a control terminal for controlling a current flow from a first terminal to a second terminal. In each oscillator stage, the anode of the diode is coupled to the first terminal of the transistor at an internal node. The control terminal of the transistor in each oscillator stage is coupled to the internal node of a proceeding oscillator stage. Further, the control terminal of the transistor in the first oscillator stage is coupled to the internal node of the last oscillator stage.

Abstract: A method for an oversampling digital-to-analog converter (DAC) includes oversampling M-bit binary data to provide N-bit oversampled binary data, wherein M and N are integers and N is greater than M, encoding the N-bit oversampled binary data to provide 2(N-1)-bit thermometer code data and a sign bit, shuffling the 2(N-1)-bit thermometer code data to provide 2(N-1)-bit shuffled data, converting the 2(N-1)-bit shuffled data and the sign bit to an analog output signal, and smoothing the analog signal to provide a smoothed analog output signal.

Abstract: An integrated oscillator circuit has a plurality oscillator stages including a first oscillator stage, an odd number of intermediate oscillator stages, and a last oscillator stage arranged in series. Each of the oscillator stages has a reverse-biased diode device and a transistor coupled in series between a power supply and a ground. Each diode device has an anode and a cathode, and each transistor has a control terminal for controlling a current flow from a first terminal to a second terminal. In each oscillator stage, the anode of the diode is coupled to the first terminal of the transistor at an internal node. The control terminal of the transistor in each oscillator stage is coupled to the internal node of a proceeding oscillator stage. Further, the control terminal of the transistor in the first oscillator stage is coupled to the internal node of the last oscillator stage.

Abstract: A self-biased RC (resistor-capacitor) oscillator and ramp generator circuit includes a combined current and voltage reference circuit for providing a reference current, a first reference voltage, and a second reference voltage. The combined current and voltage reference circuit includes a circuit branch of an NMOS transistor in a diode connection, a PMOS transistor in a diode connection, and a resistor coupled in series. The circuit also has a signal generating circuit that includes a capacitor. The signal generating circuit is configured to charge and discharge the capacitor between the first reference voltage and the second reference voltage. The self-biased RC oscillator and ramp generator circuit is configured to provide a ramp or saw tooth signal at a node of the capacitor and to provide an oscillator output signal at an output of the signal generating circuit.

Abstract: A self-biased RC (resistor-capacitor) oscillator and ramp generator circuit includes a combined current and voltage reference circuit for providing a reference current, a first reference voltage, and a second reference voltage. The combined current and voltage reference circuit includes a circuit branch of an NMOS transistor in a diode connection, a PMOS transistor in a diode connection, and a resistor coupled in series. The circuit also has a signal generating circuit that includes a capacitor. The signal generating circuit is configured to charge and discharge the capacitor between the first reference voltage and the second reference voltage. The self-biased RC oscillator and ramp generator circuit is configured to provide a ramp or saw tooth signal at a node of the capacitor and to provide an oscillator output signal at an output of the signal generating circuit.

Abstract: An integrated circuit includes an electrically resettable fuse device. The electrically resettable fuse device has a plurality of resettable fuse modules coupled in parallel. Each resettable fuse module including a fuse element characterized by a first and a second impedance states. The plurality of resettable fuse modules are configured such that when the fuse element is in the first impedance state, and a current flowing through each fuse element in a first direction exceeds a current limit, the fuse element enters into the second impedance state. When the fuse element is in the second impedance state and, in response to a global reset signal and a local reset signal, a current is applied to the fuse element in a second direction opposite the first direction, the fuse element is reset to the first impedance state.

Abstract: An integrated circuit is provided that includes an electrically resettable fuse device. The electrically resettable fuse device has a plurality of resettable fuse modules coupled in parallel. Each resettable fuse module including a fuse element characterized by a first and a second impedance states. The plurality of resettable fuse modules are configured such that when the fuse element is in the first impedance state, and a current flowing through each fuse element in a first direction exceeds a current limit, the fuse element enters into the second impedance state. When the fuse element is in the second impedance state and, in response to a global reset signal and a local reset signal, a current is applied to the fuse element in a second direction opposite the first direction, the fuse element is reset to the first impedance state.

Abstract: An integrated circuit for providing programmable microphone interface includes an input terminal for receiving an input signal and an output terminal for providing an output audio signal. The integrated circuit includes a bias circuit, an amplifier circuit, and two feedback circuits. The bias circuit provides a microphone bias signal to the microphone and provides a sensed microphone signal. The amplifier circuit includes a first input, a second input, and an output. The first input is configured to receive the sensed microphone signal, a first feedback signal, and a second feedback signal. The second input is configured to receive a first reference signal. The feedback circuits are in communication with the output and the first input of the amplifier circuit. In a specific embodiment, the first feedback circuit includes an RC circuit and the second feedback circuit includes an integrator.

Abstract: An integrated circuit for providing programmable microphone interface includes an input terminal for receiving an input signal and an output terminal for providing an output audio signal. In an embodiment, the integrated circuit includes a bias circuit, an amplifier circuit and two feedback circuits. The amplifier circuit includes a first input, a second input, and an output. The first input receives either the input signal or a feedback signal, depending upon mode control signals. The second input receives either the feedback signal or the input signal depending upon the mode control signals. The first feedback circuit is in communication with the output and the first input of the amplifier and includes a first resistor and a first capacitor connected in parallel. The second feedback circuit includes an integrator circuit and provides the feedback signal. The mode control signals can be set in a programmable mode control register.

Abstract: A subscriber line interface circuit apparatus includes a linefeed circuit and a subscriber line control circuit (SLCC). In an embodiment, the linefeed circuit includes a signal conversion circuit which provides a differential mode signal and a common mode signal in response to at least a tip signal and a ring signal from the subscriber loop. The linefeed circuit includes a tip control circuit and a ring control circuit. In an embodiment, the SLCC is provided in a single integrated circuit chip and is coupled to the linefeed circuit which isolates the SLCC from the tip or ring signals. The SLCC includes a first and a second differential mode inputs for receiving the differential mode signal, and a common-mode input for receiving the common-mode signal. In an embodiment, the SLCC also provides various tip control signals and ring control signals to the tip control circuit and the ring control circuit, respectively.

Abstract: A CMOS analog switch circuit includes an NMOS switch transistor, a PMOS switch transistor, and a bias circuit. In an embodiment, the bias circuit includes a first and a second native bias transistors having their gate terminals coupled to a first and a second terminals of the CMOS switch circuit, respectively. The source terminals of the first and the second native bias transistors are coupled together and are also coupled to the body terminal of the PMOS switch transistor. In an configuration, the first and the second native bias transistors are characterized by substantially 0V threshold voltages, and the PMOS switch transistor is configured to exhibit a lower on-resistance in response to the greater of the voltages of the first terminal and the second terminal of the CMOS analog switch circuit.

Abstract: A CMOS analog switch circuit includes an NMOS switch transistor, a PMOS switch transistor, and a bias circuit. In an embodiment, the bias circuit includes a first and a second native bias transistors having their gate terminals coupled to a first and a second terminals of the CMOS switch circuit, respectively. The source terminals of the first and the second native bias transistors are coupled together and are also coupled to the body terminal of the PMOS switch transistor. In an configuration, the first and the second native bias transistors are characterized by substantially 0V threshold voltages, and the PMOS switch transistor is configured to exhibit a lower on-resistance in response to the greater of the voltages of the first terminal and the second terminal of the CMOS analog switch circuit.

Abstract: A subscriber line interface circuit apparatus includes a linefeed circuit and a subscriber line control circuit (SLCC). In an embodiment, the linefeed circuit includes a signal conversion circuit having cross-coupled first and second MOSFETs for providing a differential mode signal and a common mode signal in response to at least a tip signal and a ring signal from the subscriber loop. The linefeed circuit includes a tip control circuit and a ring control circuit, each having two or more MOSFETs. In an embodiment, the SLCC is provided in a single integrated circuit chip and is coupled to the linefeed circuit which isolates the SLCC from the tip or ring signals. The SLCC includes a first and a second differential mode inputs for receiving the differential mode signal, and a common-mode input for receiving the common-mode signal.

Abstract: An integrated circuit for providing programmable microphone interface includes an input terminal for receiving an input signal and an output terminal for providing an output audio signal. The integrated circuit includes a bias circuit, an amplifier circuit, and two feedback circuits. The bias circuit provides a microphone bias signal to the microphone and provides a sensed microphone signal. The amplifier circuit includes a first input, a second input, and an output. The first input is configured to receive the sensed microphone signal, a first feedback signal, and a second feedback signal. The second input is configured to receive a first reference signal. The feedback circuits are in communication with the output and the first input of the amplifier circuit. In a specific embodiment, the first feedback circuit includes an RC circuit and the second feedback circuit includes an integrator.