Abstract: In a method and network component of a communications network for switching connections of low bit rate between input modules and output modules, the input modules and the output modules form a first switching level, and an ATM switching stage arranged between the input modules and the output modules forms a second switching level. In the first switching level, a number of low bit rate connections at the input module, which are to be transmitted to the same output module, are respectively merged by the input module into at least one ATM connection. In the second switching level, the switching through of the ATM connections for transmitting data in ATM cells ensues by the ATM switching stage. Subsequently, in the first switching level, the ATM connections which have been switched through are converted by the output module into the low bit rate connections.

Abstract: A micro-computer system for data processing and for the rapid location of a characteristic block has a working store which is organized so that it can be used as a conventional working store with a data width of, for example, one byte. This working store contains a data file storage zone for storing, along with other data, a plurality of blocks of multi-byte characteristics. Several read-write stores, all of which contain one or more bytes of the block of characteristics, are read out simultaneously, while the data ports of the read-write stores are cut off from the data bus. The comparison with the combinations searched for is carried out via comparators which compare the data read from the read-write stores with the combinations searched for, which are intermediately stored. The outputs of the comparators are connected to the inputs of an AND gate which produces an identity signal which terminates the searching.

Abstract: The invention relates to a multi-microcomputer system employing a direct memory access controller for direct memory access. The data buses and address buses of the several microcomputers are interconnected by means of bus separator stages which normally isolate the buses, but enable the buses to communicate with each other during data exchange between the read-write stores of the individual microcomputers. The microprocessors are switched into their HOLD state during data exchange, and the data exchange is effected via the DMA controller which is supplied with the address zones of the source and destination by a designated microcomputer. In order to increase operational reliability, two or more multi-microcomputer systems, each containing a DMA controller, can be connected in parallel.