Abstract: A telemetered characteristic monitor system includes a remotely located data receiving device, a sensor for producing signal indicative of a characteristic of a user, and a transmitter device. The transmitter device includes a housing, a sensor connector, a processor, and a transmitter. The transmitter receives the signals from the sensor and Tirelessly transmits the processed signals to the remotely located data receiving device. The processor coupled to the sensor processes the signals from the sensor for transmission to the remotely located data receiving device. The data receiving device may be a characteristic monitor, a data receiver that provides data to another device, an RF programmer for a medical device, a medication delivery device (such as an infusion pump), or the like.

Abstract: A telemetered characteristic monitor system includes a remotely located data receiving device, a sensor for producing signal indicative of a characteristic of a user, and a transmitter device. The transmitter device includes a housing, a sensor connector, a processor, and a transmitter. The transmitter receives the signals from the sensor and wirelessly transmits the processed signals to the remotely located data receiving device. The processor coupled to the sensor processes the signals from the sensor for transmission to the remotely located data receiving device. The data receiving device may be a characteristic monitor, a data receiver that provides data to another device, an RF programmer for a medical device, a medication delivery device (such as an infusion pump), or the like.

Abstract: An on-chip FPN calibration method and circuits scheme applying a reference voltage signal to an array of calibration pixels coupled to a sensor matrix. Two data values are read from each bit line and used to calculate an offset and a gain error for a pixel column. A reference offset and a reference gain error value are then generated by computing the average offset and the average gain error from the collected offset and gain error values of each bit line. Calibration data for each bit line then comprises an offset difference and a gain error difference, the offset difference comprising the difference between the offset value for that bit line and the reference offset, and the gain error difference comprising the gain error difference between the gain error for that bit line and the reference gain error. The calibration data for each bit line is then stored in on-chip volatile memory and is used later under normal operation to compensate for the FPN effect.

Abstract: A marketplace that facilitates the business of education finance by providing a globally accessible exchange that facilitates transactions between educational institutions and lenders, and between loan sellers and loan buyers. Specifically, the present invention provides a system and method for selecting a preferred lender list, and a system and method for selling loan portfolios and forward purchase commitments. The present invention also provides a system and method for conducting an auction over a global computer network (e.g., the Internet), which enables the offer or that posts the auction to choose, after receiving proposals, whether to select bidders that qualify for a second round of bidding and continue with bidding, or award winners and conclude the auction.

Abstract: Disclosed is an image sensor including one or more dummy pixels that produce a reference signal which is used to compensate for errors within the devices of the main pixel cells. In one embodiment, at least one dummy pixel is used in conjunction with other circuitry to correct for nonlinearities in the transfer characteristic of a source follower transistor within each pixel. In another embodiment, an array of dummy pixels is used to correct for leakage current within the pixels during an electronic shutter mode of operation. The two techniques can be combined whereby both threshold voltage mismatch and leakage current are compensated for.

Abstract: The present invention relates to an automatic gain control circuit in which the automatic gain control function is performed entirely in the digital domain. In an illustrative embodiment, the digital automatic gain control circuit for an image sensor having associated therewith an analog-to digital (A/D) converter for converting analog electrical signals from the image sensor to corresponding digital codes, includes a min/max detector for determining minimum and maximum electrical signal values from the digital codes of the A/D converter for each frame of image. A filter coupled to the min/max detector dampens instantaneous changes of the minimum and maximum values by filtering to provide filtered minimum and maximum values.

Abstract: A low-power column parallel ADC architecture for image sensors that reduces the power consumption by reducing the number of switchings of a comparator to digitize a row of pixel data. Two ramp reference signals are provided in accordance with the principles of this invention. A first ramp signal is provided to each comparator that is clocked with an associated first clock signal. In each column comparator, the first ramp signal is compared to the pixel data using clock1, wherein clock1 corresponds to N multiple of a second clock signal (clock2), with N>1. Only when the column comparator detects a first crossover with the first ramp signal, then the comparator switches at every clock cycle of the second clock, clock2, to compare and detect a second crossover point with the second reference signal. This arrangement can greatly reduce the number of switchings required to digitize a row of pixel data, thereby resulting in significant power saving.

Abstract: A CMOS image sensor is provided in which correlated double sampling is performed entirely in the digital domain. In an exemplary embodiment, the image sensor includes a plurality of imager cells arranged in rows and columns, where the imager cells of a particular column are coupled to a column data line of that column. Each active imager cell is capable of selectively providing a first output on an associated column data line indicative of a reset level during a first sampling interval. During a second sampling interval, each active imager cell provides a signal output on the associated column data line indicative of an amount of light incident upon that imager cell. At least one analog to digital (A/D) converter is coupled to the column data lines and converts the first and signal outputs on each column data line to first and second digital codes, respectively, to complete a correlated double sampling operation. The invention eliminates the need for analog capacitors to store the reset and signal levels.

Abstract: Disclosed is an image sensor having A/D conversion circuitry coupled to column data lines of an image sensor array. The A/D conversion circuitry digitizes analog signals on the column data lines, each representing intensity of light incident upon an active imager cell. Higher resolution is provided for darker light levels than for bright light levels, such that a high resolution image is obtained with less storage data than would otherwise be required. In one embodiment, the A/D conversion circuitry includes a plurality of comparators, each having a first input coupled to one or more column data lines and a second input coupled to receive a time-varying reference signal, and a plurality of n-bit counters coupled to the comparator outputs. An n-bit to m-bit converter nonlinearly maps n-bit codes to m-bit codes and provides the m-bit codes to an m-bit D/A converter which produces the time-varying reference signal.

Abstract: Disclosed is an image sensing device having a reduced number of transistors within each imager cell as compared to prior art devices. Each imager cell includes a photosensitive element providing a photocharge responsive to incoming light, and first, second and third transistors. The first transistor is coupled to an activation line, e.g., a row select line, that carries an activation signal to a first plurality of imager cells to selectively activate cells for image data readout. This transistor transfers the photocharge towards a reference circuit node within the image cell in response to the activation signal. The second transistor is operably coupled to the first transistor, and is operative to selectively set a voltage level at the reference node. The third transistor has a control terminal coupled to the reference node, and an output terminal coupled to an output data bus common to a second plurality of image cells, e.g., a column of cells.

Abstract: Disclosed is a circuit for performing correlated double sampling entirely in the digital domain. In an exemplary embodiment, the circuit includes a plurality of comparators, each having a first input coupled to an associated data line for receiving first and second signals in first and second sampling intervals, respectively. A time varying reference signal is applied to the second input of each comparator. A plurality of up/down counters are coupled to respective ones of the comparators, and each is operable to count in a first direction during the first sampling interval and in an opposite direction during the second sampling interval. Each up/down counter is caused to stop counting when the amplitude of the variable reference signal substantially equals the amplitude of the respective first or second signal. As a result, each up/down counter provides an output representing a subtraction of one of said first or second signals from the other.

Abstract: A self-biased, fully differential, complementary receiver apparatus and method is presented. The receiver accepts differential inputs that can vary over the full rail-to-rail common mode voltage range. It produces double-ended complementary outputs swinging rail-to-rail useful in signal level conversion and comparator applications. The receiver includes a dual, fully complementary and mirror-symmetrical arrangement of a differential input stage, a biasing stage and an output stage. A self biasing voltage is generated with a balanced voltage divider coupled between the outputs of the biasing stages. This frees both biasing outputs for use as analogous but complementary receiver outputs while providing the receiver with all the advantages of self bias. For small signal differential inputs, the input and biasing stages operate in their linear region useful for amplifier applications.